What is it about?
The programmable parser is a key component of programmable switches ASIC and FPGA-based SmartNIC, but throughput higher than 1.6Tbps is fairly challenging. Hyperparser achieves a throughout higher than 1.6Tbps by adopting the butterfly network.
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Why is it important?
A single instance of ASIC-based HyperParser can achieve 3.2-6.8 Tbps, while previous work can hardly achieve a throughput higher than 1Tbps. This may become a bottleneck for the coming 1.6T Ethernet.
Perspectives
I'm glad to share my idea with the community, and the source code of HyperParser has been released on Github.
Huan Liu
Xidian University
Read the Original
This page is a summary of: HyperParser: A High-Performance Parser Architecture for Next Generation Programmable Switch and SmartNIC, June 2021, ACM (Association for Computing Machinery),
DOI: 10.1145/3469393.3469399.
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