What is it about?

For RISC-V, an open-source CPU specification, a massive number of additional features (instruction extensions) have been proposed and ratified, but many are not yet implemented in actual hardware. To address this, we built a lightweight virtualization software (Type-1 hypervisor) from scratch to preemptively run these new features on existing real hardware. Additionally, we developed a tool that automatically generates the necessary program components (such as decoders and module templates) for emulating these extensions directly from the CPU's specification description language.

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Why is it important?

Currently, there are over 150 useful extensions created for RISC-V. However, due to implementation costs and the difficulty of predicting demand, only about 30% of them are actually available on physical boards. This creates a classic "chicken-and-egg" problem: you cannot build software without the hardware, and you cannot build hardware without the software to prove the demand. Our system provides an environment where you can easily test future features on real hardware today. This dramatically accelerates the entire development cycle, from designing new specifications and verifying software to the eventual transition to hardware manufacturing.

Perspectives

This project started from a personal struggle: as a fan of RISC-V and system software, I wanted to try out various RISC-V features on real hardware, but such boards were rarely available on the market. With support from a national incubation project, I developed a hypervisor supporting the RISC-V H extension from scratch, gradually adding emulation capabilities and modular features. The number of RISC-V extensions continues to grow, and real hardware supporting various extensions is slowly but steadily increasing. I hope this research will contribute, even a little, to the advancement of the RISC-V community.

Norimasa Takana
Tsukuba Daigaku

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This page is a summary of: Hikami: A Lightweight Hypervisor for Emulating RISC-V Extension Semantics with Sail-Driven Auto-generation, June 2026, ACM (Association for Computing Machinery),
DOI: 10.1145/3814943.3816171.
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