What is it about?
Modern FPGAs increasingly use High-Level Synthesis (HLS) to turn C/C++ code into hardware designs, making development faster and more accessible. However, this also introduces new security risks — especially from hidden hardware Trojans that may activate only under rare, hard-to-trigger conditions. GreyConE+ is a specialized test-generation framework that automatically discovers these rare vulnerabilities. Unlike traditional random testing, it learns which input conditions are most likely to expose hidden malicious behavior, reducing detection time by up to 7.2×. This work helps chip designers, security analysts, and tool developers improve trust and reliability in FPGA-based systems — especially in defense, finance, edge computing, and critical infrastructure, where hardware security is essential.
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This page is a summary of: GreyConE+: Efficient Rare-Target Test Generation for FPGA HLS Designs, ACM Transactions on Reconfigurable Technology and Systems, November 2025, ACM (Association for Computing Machinery),
DOI: 10.1145/3769295.
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