Consistency Constraints for Code Generation for BED Processor Architectures

What is it about?

We envision a new class of processor architectures named buffered exposed datapath (BED) architectures. They provide (scalable) queues at datapaths between their execution units, enabling these units to directly communicate computed values with one another. They further expose these buffered datapaths to the compilers so that the compilers can organize this direct data communication between the execution units for program execution. Our article describes consistency constraints that must be met by the code generated by compilers for these novel architectures. Understanding these constraints will allow us to design new compilers and processors for better execution performance of sequential programs by more effectively exploiting the instruction-level parallelism contained in these programs.

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Photo by Alexandre Debiève on Unsplash

Photo by Alexandre Debiève on Unsplash

Why is it important?

Since processor clock speeds have been nearly stagnant for two decades, it is important to increase the utilization of parallelism contained in sequential programs to improve their execution performance on processors. Modern processors can execute many instructions in parallel even from sequential programs. However, their internal organization restricts the extent to which this instruction-level parallelism can be utilized. A major factor is the use of (poorly scaling) central local storage (in the form of a limited number of registers closest to the processor and caches at the next levels) by their execution units to store and communicate computed values. Moreover, the compilers focus on generating code that uses as few registers as possible, further limiting processors' potential to exploit instruction-level parallelism.

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