What is it about?

We envision a new class of processor architectures named buffered exposed datapath (BED) architectures. They provide (scalable) queues at datapaths between their execution units, enabling these units to directly communicate computed values with one another. They further expose these buffered datapaths to the compilers so that the compilers can organize this direct data communication between the execution units for program execution. Our article describes consistency constraints that must be met by the code generated by compilers for these novel architectures. Understanding these constraints will allow us to design new compilers and processors for better execution performance of sequential programs by more effectively exploiting the instruction-level parallelism contained in these programs.

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Why is it important?

Since processor clock speeds have been nearly stagnant for two decades, it is important to increase the utilization of parallelism contained in sequential programs to improve their execution performance on processors. Modern processors can execute many instructions in parallel even from sequential programs. However, their internal organization restricts the extent to which this instruction-level parallelism can be utilized. A major factor is the use of (poorly scaling) central local storage (in the form of a limited number of registers closest to the processor and caches at the next levels) by their execution units to store and communicate computed values. Moreover, the compilers focus on generating code that uses as few registers as possible, further limiting processors' potential to exploit instruction-level parallelism.


This article is perhaps one of the first papers on the topic to specify the criteria that the code generated by compilers for architectures with buffered exposed datapaths must meet. However, generating optimal code that maximally exploits instruction-level parallelism is very expensive, so future work will need to develop heuristics based on the foundations established in this article. Therefore, we believe that many future papers can refer to this article to describe the general conditions that must be fulfilled.

Anoop Bhagyanath
RPTU Kaiserslautern-Landau

Read the Original

This page is a summary of: Consistency Constraints for Mapping Dataflow Graphs to Hybrid Dataflow/von Neumann Architectures, ACM Transactions on Embedded Computing Systems, July 2023, ACM (Association for Computing Machinery),
DOI: 10.1145/3607869.
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