What is it about?

FPGAs are increasingly being used in cloud infrastructures for accelerating large-scale data processing. Yet, any engineer who has ever used an FPGA knows how complicated the programming models are, compared to writing software. This complexity, being a natural outcome of dealing with reconfigurability in hardware, is not easy to avoid. Nevertheless, we think that with the right abstraction layers, spanning both hardware and software, we can reach a programming model that makes FPGA-based accelerators easier to develop and deploy, while maintaining high performance. Our aim with this work was to take a step in finding these abstraction layers: We argue, that on the FPGA we need a layer that is an intermediate point between a fully specialized circuit and a general purpose processor. With that in place, we show how to augment the system level functionality to the point where it is somewhat comparable to that of a conventional operating system in terms of thread management, but for FPGA-based accelerators.

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Why is it important?

The complex programming models for FPGAs are harmful for these otherwise very capable devices in many ways: (1) The development effort is often orders of magnitude higher compared to software. (2) The applicability of accelerators are very often limited to a single task. (3) The deployment is rigid, where the system's interaction with the accelerators is mainly triggering it and waiting until its completion. These limitations are hindering the usefulness of FPGAs especially in cloud use cases, where rapid development, targeting varied application domains, and deployment flexibility/virtualization are crucially important. Our work takes a step in the direction where we show fundamental ways to lift these limitations.

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This page is a summary of: PipeArch, ACM Transactions on Reconfigurable Technology and Systems, December 2020, ACM (Association for Computing Machinery),
DOI: 10.1145/3418465.
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