High order wafer alignment for 20nm node logic process

Bumhwan Jeon, Shyam Pal, Sohan Mehta, Subramany Lokesh, Yun Tao Jiang, Chen Li, Mark Yelverton, Yayi Wei
  • April 2013, SPIE
  • DOI: 10.1117/12.2010709
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The following have contributed to this page: Mr. Sohan S Mehta