What is it about?
In this paper, power-aware signal integrity (PI-SI) analysis of data group signals of an onboard DDR4 memory module using power-aware IBIS model is presented. DDR4 power plane and data signals are analyzed using 3D Electromagnetic based PI-SI solver then the transient simulation is performed on combined PI data of power plane and data signals to get simultaneously switching noise (SSN) response of data bus and crosstalk between nearby channels.
Featured Image
Photo by Frank Wang on Unsplash
Why is it important?
Power-Aware signal integrity analysis of DDR4 data bus is necessary for the channel reliability and robustness. In highspeed digital (HSD) boards due to simulation tools limitation, power integrity, and signal integrity analysis are performed separately. The complete data channel performance is the cumulative effect of whole interconnect environment that consists of transceiver ICs, power planes, bond wires, board substrate, data lines and board interconnects that's why it's necessary to consider power plane generated noise effect in data channel signal integrity analysis.
Perspectives
SI engineers do power-aware SI analysis of channel to ensure proper and reliable operation using Electronic Design Automation tools (EDA) before actual fabrication of board. This reduces board failure chances significantly and also cut production time.
RF | Microwave | Antenna | Signal Integrity Engineer Anil Pandey
Keysight Technologies
Read the Original
This page is a summary of: Power-aware signal integrity analysis of DDR4 data bus in onboard memory module, May 2016, Institute of Electrical & Electronics Engineers (IEEE),
DOI: 10.1109/sapiw.2016.7496261.
You can read the full text:
Resources
Contributors
The following have contributed to this page
