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Per-core vector support in multicores is not efficient since applications rarely sustain high DLP. We present two Power Gating (PG) schemes to dynamically control Vector co-Processors (VPs) shared by cores. ASIC and FPGA modeling show that PG can reduce the energy by 33% while maintaining high performance.
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This page is a summary of: Efficient on-chip vector processing for multicore processors, October 2013, Institute of Electrical & Electronics Engineers (IEEE),
DOI: 10.1109/issoc.2013.6675260.
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