The hierarchical concurrent flow graph approach for modeling and analysis of design processes

V. Sahula, C.P. Ravikumar
  • Institute of Electrical & Electronics Engineers (IEEE)
  • DOI: 10.1109/icvd.2001.902645

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http://dx.doi.org/10.1109/icvd.2001.902645

The following have contributed to this page: Professor Vineet Sahula