What is it about?
This paper proposed techniques for implementing complete TMR circuits on an FPGA so that they could be more rapidly recovered from errors while significantly saving energy consumed in recovering from errors.
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This page is a summary of: Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration, September 2013, Institute of Electrical & Electronics Engineers (IEEE),
DOI: 10.1109/fpl.2013.6645571.
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