What is it about?

This paper proposes a general design principle of a single-carrier-based pulse width modulation (SC-PWM) technique for a uniform step, asymmetrical multilevel converter with k series-connected H-bridge inverters under unequal DC-link voltages within each phase. The proposed modulation approach is a straightforward implementation of the conventional phase disposition PWM. It may produce many output voltage levels (any odd number between 2k+1 and 3k) using only one carrier signal without complicating its implementation scheme. This makes it suitable for real-time implementation in available low-cost microcontrollers and microprocessors. The topological structure of the investigated asymmetrical multilevel converter is presented, and analytical relationships are established to define a general design principle of a uniform step configuration. Then, the proposed method's working principle and its generalized implementation scheme are presented and discussed. The effectiveness of the suggested PWM technique is finally demonstrated by simulation and experimental results for a single-phase, three-cell asymmetric converter operating under unequal DC-link voltages with 7, 11, 13, and 15 voltage levels

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Why is it important?

The overall proposed SC-PWM scheme requires only addition and subtraction operations and one comparator block, which reduces the complexity of its implementation in commonly used low-cost digital control boards. The applicability and suitability of the suggested SC-PWM approach were simulated and tested using an asymmetrical multilevel converter with 3 cells per phase operating under different DC-link voltage conditions.

Perspectives

For the future work, the proposed SC-PWM method can be improved by including an optimized switching function for balancing switching losses among H-bridge cells

Dr Fils Pascal Mpomboum Lingom
Baylor University

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This page is a summary of: A Single-Carrier PWM Method for Uniform Step Asymmetrical Multilevel Converters, October 2023, Institute of Electrical & Electronics Engineers (IEEE),
DOI: 10.1109/ecce53617.2023.10362685.
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