A 1.6–880MHz synthesizable ADPLL in 0.13um CMOS

  • Hsiang-Hui Chang, Shang-Ming Lee, Chao-Wen Chou, Yu-Tung Chang, Yi-Li Cheng
  • April 2008, Institute of Electrical & Electronics Engineers (IEEE)
  • DOI: 10.1109/vdat.2008.4542400

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http://dx.doi.org/10.1109/vdat.2008.4542400