3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

  • Yann Civale, Deniz Sabuncuoglu Tezcan, Harold G. G. Philipsen, Fabrice F. C. Duval, Patrick Jaenen, Youssef Travaly, Philippe Soussan, Bart Swinnen, Eric Beyne
  • IEEE Transactions on Components Packaging and Manufacturing Technology, June 2011, Institute of Electrical & Electronics Engineers (IEEE)
  • DOI: 10.1109/tcpmt.2011.2125791

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