An FPGA Implementation of a Competitive Hopfield Neural Network for Use in Histogram Equalization

  • S.M. Saif, H.M. Abbas, S.M. Nassar, S.M. Saif, H.M. Abbas
  • Institute of Electrical & Electronics Engineers (IEEE)
  • DOI: 10.1109/ijcnn.2006.1716479

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http://dx.doi.org/10.1109/ijcnn.2006.1716479