A 14-mW, 153.6-MHz clock-rate Δ∑ modulator for WCDMA with 77-dB SFDR using constant resistance CMOS input sampling switch

Olujide A. Adeniran, Andreas Demosthenous
  • September 2007, Institute of Electrical & Electronics Engineers (IEEE)
  • DOI: 10.1109/esscirc.2007.4430289

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http://dx.doi.org/10.1109/esscirc.2007.4430289