Layout-to-schematic as a step towards layout-versus-schematic verification of SFQ integrated circuit layouts

Rebecca M. C. Roberts, Coenrad J. Fourie
  • September 2013, Institute of Electrical & Electronics Engineers (IEEE)
  • DOI: 10.1109/afrcon.2013.6757839

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http://dx.doi.org/10.1109/afrcon.2013.6757839