Modeling of interconnect capacitance, delay, and crosstalk in VLSI

  • Shyh-Chyi Wong, Gwo-Yann Lee, Dye-Jyun Ma
  • IEEE Transactions on Semiconductor Manufacturing, January 2000, Institute of Electrical & Electronics Engineers (IEEE)
  • DOI: 10.1109/66.827350

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http://dx.doi.org/10.1109/66.827350