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Charge simulation method is used to obtain the design dimensions of a high voltage capactior for the permissible design stress. The final dimensions are verified through moment of methods and fabricated. The experimental measurement of capacitance is carried out.

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This page is a summary of: Design of an HV capacitor using the inherent advantage of charge simulation method and experimentations, IET Science Measurement & Technology, January 2018, the Institution of Engineering and Technology (the IET),
DOI: 10.1049/iet-smt.2017.0121.
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