Adapted Near-State PWM for D2L Inverters for Reducing Common-Mode Voltage and Switching Losses
What is it about?
A near-state pulse width modulation (NSPWM) algorithm is proposed and implemented on dual two-level voltage source inverters (D2L-VSIs) in order to reduce common-mode voltage (CMV), the inverter switching losses, current total harmonic distortion (THD), and the side effects of bearing currents compared to SVM and PWM7. In order to gain these goals, two conventional two-level (2L) inverters of the D2L-VSI are controlled, separately, with specific switching sequences and an adjusted phase difference between the carriers (PDC) of two inverters. For evaluating and comparing these PWM techniques mathematically, D2L-VSI’s both CMV root mean square (CMV-RMS) generated and switching losses are formulated as a function of the power factor (PF) of the D2L-VSI, which is driven by the methods detailed in this manuscript. Eventually, theories and analysis, as well as simulations and experimental results which are generated by MATLAB/Simulink environment and a 300W scaled-down D2L-VSI prototype respectively, authenticate the superiority of the proposed NSPWM over both SVM and PWM7.
Why is it important?
Our methodology reduces common-mode voltage (CMV), the inverter switching losses, current total harmonic distortion (THD), and the side effects of bearing currents compared to what is produced by SVM and PWM7.
The following have contributed to this page: Dr Hamed Nafisi, Amir Aghazadeh, and Masoud Davari
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