What is it about?
Design principles of CDDK domino circuit which offer high-speed performance and the speed performance is less affected by the variations in the manufacturing process
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Why is it important?
The need for compact and fast systems demand compactness of circuit with the limited number of transistors led to a novel CDDK domino topology. In addition, the robustness of the circuit is also enhanced due to the feedback keeper topology arrangement.
Perspectives
The research article provides an elaborative explanation on the design constraints to achieve high -speed performance.
Anita Angeline A
VIT Chennai
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This page is a summary of: Design Impacts of Delay Invariant High Speed Clock Delayed Dual Keeper Domino Circuit, IET Circuits Devices & Systems, July 2019, the Institution of Engineering and Technology (the IET),
DOI: 10.1049/iet-cds.2018.5410.
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