What is it about?
A highly synthesizable analog voltage comparator is presented which consists of CMOS-based standard cells. The comparator is implemented on a flexible device to extend the use of automated synthesis and digital gate methodology in the analog design. Due to its digital design methodology, the proposed comparator is enormously cost-effective, reduces the time to market, scalable to newer technologies and more immune to process variations that the conventional CMOS voltage comparators.
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Why is it important?
Due to its digital design methodology, the proposed comparator is enormously cost-effective, reduces the time to market, scalable to newer technologies and more immune to process variations that the conventional CMOS voltage comparators.
Perspectives
It gives a path to see the fully differential analog comparator working in FPGAs.
Anil Singh
Thapar Institute of Engineering and Technology
Read the Original
This page is a summary of: A Highly-Digital Voltage Scalable 4-bit Flash ADC , IET Circuits Devices & Systems, July 2018, the Institution of Engineering and Technology (the IET),
DOI: 10.1049/iet-cds.2018.5148.
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