What is it about?
Included in our study are two proposed techniques. These techniques can be implemented to drastically improve the efficiency and scalability of formal equivalence verification targeted at NCL circuits.
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This page is a summary of: Abstraction techniques to improve scalability of equivalence verification for NCL circuits, Electronics Letters, September 2016, the Institution of Engineering and Technology (the IET),
DOI: 10.1049/el.2016.1138.
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