Efficient CMOS subthreshold leakage analysis with improved stack based models in presence of parameter variations

L. Garg, V. Sahula
  • Electronics Letters, May 2013, the Institution of Engineering and Technology (the IET)
  • DOI: 10.1049/el.2012.4311

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http://dx.doi.org/10.1049/el.2012.4311

The following have contributed to this page: Professor Vineet Sahula