Signal flow graphs for modelling of switching converters with reduced redundant power processing

  • R. Loera-Palomo, J. Leyva-Ramos, J.A. Morales-Saldaña
  • IET Power Electronics, August 2012, the Institution of Engineering and Technology (the IET)
  • DOI: 10.1049/iet-pel.2012.0038

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http://dx.doi.org/10.1049/iet-pel.2012.0038

The following have contributed to this page: Dr. Rodrigo Loera-Palomo