What is it about?

Asynchronous quasi-delay-insensitive (QDI) circuits have recently become an active research area in digital logic design. In contrast with synchronous paradigms, QDI approaches utilise threshold gates with hysteresis, such as Muller C-element and null convention logic (NCL) gates. However, there are no existing methods to explicitly describe these hysteretic logic gates in Boolean algebra. Therefore, in this paper, we extend the Boolean algebra with two novel operators, named completion and truth tuple, to enable explicit expressions for all QDI elements such as C-elements, NCL, NCL+, latches and several non-conventional hysteretic threshold gates that we call dual-threshold logic. In addition, we develop a set of 16 laws and theorems for these new operators to create a complete novel algebraic extension for QDI logic

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Why is it important?

It is demonstrated that our extended algebra is a complete approach for explicit design and analysis of QDI circuits including logic description, equation formation from truth table, expression simplification and conversion, and even gate mapping and corresponding CMOS implementation. We also provide an analysis and solution for netlist corruption problems during the synthesis process of existing QDI design flows, as well as a complete design example using the extended Boolean algebra with different QDI design styles.

Perspectives

Although the QDI asynchronous logic has been being researched for numerous decades, its theory and practice are still not popular outside of the academic and research world. In fact, the design and analysis of those circuits is still a challenge for those people who have just entered this field. Therefore, our work is aimed to provide a comprehensive and ease-of-use algebraic approach for this type of circuit. We hope that with our approach, the QDI asynchronous logic now will be an easy-to-understand concept as conventional synchronous circuits.

Linh Duc Tran

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This page is a summary of: Extended Boolean algebra for asynchronous quasi-delay-insensitive logic, IET Circuits Devices & Systems, August 2020, the Institution of Engineering and Technology (the IET), DOI: 10.1049/iet-cds.2020.0062.
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