Calibration of gain and timing errors for time-interleaved ADCs
What is it about?
Although time-interleaved ADCs is efficient for high-speed applications, they are vulnerable to the mismatches between the sub-ADCs. Most conventional calibration method treat each kind of mismatch source seperately, which may result in high hardware cost. We have presented a joint-calibration architecture which can deal with the gain and timing mismatches together. Becuase of reusing the circuit blocks, much hardware cost can be saved.
Why is it important?
For very high speed time interleaved ADCs (e.g. ADCs with sampling rate higher than 1GSPS), the hardware cost ane power consumpiton contributed by the calibration circuit is often huge. It is very important the lower hardware cost (e.g. the chip area) and power consumption for these applications.
The following have contributed to this page: Jie Zhang and hong zhang