Joint Background Calibration of Gain and Timing Mismatch Errors with Low Hardware Cost for Time-Interleaved ADCs

  • Hong Zhang, Jie Zhang, Bo Yang, Ruizhi Zhang
  • IET Circuits Devices & Systems, September 2018, the Institution of Engineering and Technology (the IET)
  • DOI: 10.1049/iet-cds.2018.5194

Calibration of gain and timing errors for time-interleaved ADCs

What is it about?

Although time-interleaved ADCs is efficient for high-speed applications, they are vulnerable to the mismatches between the sub-ADCs. Most conventional calibration method treat each kind of mismatch source seperately, which may result in high hardware cost. We have presented a joint-calibration architecture which can deal with the gain and timing mismatches together. Becuase of reusing the circuit blocks, much hardware cost can be saved.

Why is it important?

For very high speed time interleaved ADCs (e.g. ADCs with sampling rate higher than 1GSPS), the hardware cost ane power consumpiton contributed by the calibration circuit is often huge. It is very important the lower hardware cost (e.g. the chip area) and power consumption for these applications.

Perspectives

hong zhang
Xi'an Jiaotong University

Writing this article was a great pleasure as it has co-authors with whom I have had long standing collaborations. I hope this article is useful for those engineers who are designing time-interleaved high speed ADCs.

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http://dx.doi.org/10.1049/iet-cds.2018.5194

The following have contributed to this page: Jie Zhang and hong zhang