Methodology of elementary negative group delay active topologies identification

Blaise Ravelo
  • IET Circuits Devices & Systems, May 2013, the Institution of Engineering and Technology (the IET)
  • DOI: 10.1049/iet-cds.2012.0317

The authors haven't finished explaining this publication. If you are the author, sign in to claim or explain your work.

Read Publication

http://dx.doi.org/10.1049/iet-cds.2012.0317

The following have contributed to this page: Dr Blaise Ravelo

In partnership with: