Pipelined Extended-Counting Incremental Delta-Sigma for 3D-Stacked CMOS Image Sensors

What is it about?

CMOS image sensors (CIS) are everywhere today, in mobile phones, tablets, surveillance, autonomous cars and biometrics devices. It is becoming a common part of today’s modern society, and further development of imagers is undeniable to be expected in even more applications, such as real-time robotics, industry 4.0, ambient-assisted homes, etc. Additionally, consumer and industry demands are increasingly getting larger and more demanding in terms of spatial resolution, frame rate, dynamic range and power, as well as robustness. This poses a challenge for research to continuously innovate and to improve all these imager performances simultaneously. Generally, a CIS imager system consists of optics, a pixel array, pixel readout circuitry with the analog-to-digital converters (ADCs), and a digital processing unit. Besides the pixel size and noise, the analog-to-digital conversion is typically responsible for the overall performance limitations in CMOS imagers and also largely determines the power consumption, especially for higher specifications. An incremental ΔΣ is an excellent candidate for low-noise operation due to its oversampling and noise-shaping capability. However, state-of-the-art incremental ΔΣ ADCs for image sensors only achieve moderate speeds. In this paper, a novel incremental ΔΣ ADC architecture is being proposed in order to achieve faster conversion speeds.

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Why is it important?

Besides good noise performances and conversion time of the proposed incremental ΔΣ, motion artifacts such as discontinuous rolling shutter are mitigated by the architecture proposed in this paper. These properties are useful for machine vision applications.

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