What is it about?
Frequency domain signal processing is inevitable in almost all signal processing applications. Fast Fourier Transform (FFT) based implementation of Discrete Fourier transform calculation is a major computation unit in almost all digital signal processing systems. Pipelined FFT architecture is the best choice for high-speed systems. This paper focusses on the design of non-powers-of-two pipelined FFT systems that support multiple FFT lengths defined in the 3GPP-LTE standard.
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Why is it important?
Our findings minimize the hardware complexity of implementing non-powers-of-two pipelined FFT systems. The proposed reconfigurable 2, 3 and 5-point DFT processing element effectively shares the computational unit of the processing element using multiplexers preserving the throughput of single delay feedback (SDF) structure
Perspectives
I am very glad to write this article along with the collaborator who has supported this work with me for such a long period. The contribution in this article will effectively reduce the hardware complexity of FFT Systems
Mr Bibin Sam Paul Samuel Robinson
National Institute of Technology Tiruchirappalli
Read the Original
This page is a summary of: Reconfigurable 2, 3 and 5-point DFT processing element for SDF FFT architecture using Fast Cyclic Convolution algorithm, Electronics Letters, March 2020, the Institution of Engineering and Technology (the IET),
DOI: 10.1049/el.2019.4262.
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