What is it about?
Vernier Time-to-Digital Converters (TDC) are used to measure the time between two signals. One of the challenges is to minimize the power consumption to integrate multiple TDCs for one detector to improve its timing resolution. The letters presents a new architecture of the prelogic circuit that allows to minimize the power consumption of the circuit without impacting the timing resolution and timing jitter of the TDC.
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Why is it important?
One of the application that requires many TDC with high timing jitter is positron emission tomography scanner. This work is done in accordance to the LabPET scanners developments. For each 1.1 x 1.1 mm2 photodetector, the power budget of the TDC is 2 mW for 64 TDCs, which set a power consumption of 31 uW per TDC. This new architecture allowed the TDC to obtain a 22 uW power consumption compared to 160 uW in the previous TDC architecture.
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This page is a summary of: A 22μW, 5.1 ps LSB, 5.5 ps RMS Jitter Vernier Time-to-Digital Converter in CMOS 65 nm for Single Photon Avalanche Diode Array, Electronics Letters, February 2020, the Institution of Engineering and Technology (the IET),
DOI: 10.1049/el.2019.4105.
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