Oxide Impurities in Silicon Oxide Intermetal Dielectrics and Their Potential to Elevate Via-Resistances

Wentao Qin, Donavan Alldredge, Douglas Heleotes, Alexander Elkind, N. David Theodore, Peter Fejes, Mostafa Vadipour, Bill Godek, Norman Lerner
  • Microscopy and Microanalysis, May 2014, Cambridge University Press
  • DOI: 10.1017/s1431927614000865

Semiconductor via resistance increase due to impurities trapped in dielectrics between metal layers

What is it about?

Silicon oxide dielectrics are laid down between metal layers in microelectronic chips. The dielectrics are exposed to solutions in the washing and cleaning during the making of the chips. The solutions would introduce moisture and other impurities to the dielectrics. In addition, if the reactions to form the dielectrics are not completed, impurities are also trapped in the dielectrics. These impurities will be released to oxidize the Ti glue layer that helps the tungsten via to stick to the dielectric. Once oxidized, the Ti layer becomes more resistant to the flow of current, making the via fail the electrical requirement that can eventually fail the chip.

Why is it important?

It explains a common failure mechanism of microelectronic chips, and introduces methods to prevent the failure.

Perspectives

Wentao Qin Qin (Author)

This papers has a good combination of material science and transmission electron microscopy. Materials science has the accurate aim with the aid of TEM, and my expertise of TEM ensures that the application of materials science hits the correct target. It marks the unification of both disciplines .

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