Semiconductor via resistance increase due to impurities trapped in dielectrics between metal layers
What is it about?
Silicon oxide dielectrics are laid down between metal layers in microelectronic chips. The dielectrics are exposed to solutions in the washing and cleaning during the making of the chips. The solutions would introduce moisture and other impurities to the dielectrics. In addition, if the reactions to form the dielectrics are not completed, impurities are also trapped in the dielectrics. These impurities will be released to oxidize the Ti glue layer that helps the tungsten via to stick to the dielectric. Once oxidized, the Ti layer becomes more resistant to the flow of current, making the via fail the electrical requirement that can eventually fail the chip.
Why is it important?
It explains a common failure mechanism of microelectronic chips, and introduces methods to prevent the failure.
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