Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support

Manish Kumar Jaiswal, Ray C.C. Cheung
  • Microelectronics Journal, May 2013, Elsevier
  • DOI: 10.1016/j.mejo.2013.02.021

The authors haven't yet claimed this publication.

Read Publication

http://dx.doi.org/10.1016/j.mejo.2013.02.021