Designing and Implementing a Novel Single IFFT Scrambling PAPR Reduction Scheme in OFDM Systems Using FPGA with Hardware Co-simulation

What is it about?

This paper presents a novel low complexity technique for reducing the peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing systems followed by an efficient hardware co-simulation implementation of this technique by using a Xilinx system generator on field programmable gate array. Unlike the conventional scheme, the proposed technique requires only a single IFFT block and M iterations.

Featured Image