What is it about?
This paper presents reconfigured dual-memory controller-based VLSI architecture for discrete wavelet transform to meet the wide variety of diverse computing requirements of the future generation system on chip designs.
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Why is it important?
The proposed architecture mainly consists of a reconfigured DWT processor with dedicated memory which enhances the overall performance of the design.
Perspectives
The performance is compared with the available architectures showing good agreements. The area utilized by the DWT architecture is 13%, the delay is 11.577 ns, and the total on-chip power consumption is 23.8mW. The number of slice LUTs and slice registers utilized for the design is 912 and 1469, respectively.
Dr. ARUN SADANAND TIGADI
Read the Original
This page is a summary of: Reconfigured VLSI Architecture for Discrete Wavelet Transform, January 2019, Springer Science + Business Media,
DOI: 10.1007/978-981-13-3393-4_72.
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