All Stories

  1. 0.97 mW/Gb/s, 4 Gb/s CMOS clock and data recovery IC with dynamic voltage scaling

    Article • IET Circuits Devices & Systems, May 2016, the Institution of Engineering and Technology (the IET)

    Prof Sangjin Byun

  2. 1 ∼ 3GHz VCO with rail-to-rail VCONT range

    Article • IEICE Electronics Express, January 2016, Institute of Electronics, Information and Communications Engineers (IEICE)

    Prof Sangjin Byun

  3. Analysis and Verification of DLL-Based GFSK Demodulator Using Multiple IF-Period Delay Line

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, January 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof Sangjin Byun

  4. Analysis and Design of CMOS Received Signal Strength Indicator

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof Sangjin Byun

  5. Closed-Form Equation of Data Dependent Jitter in First Order Low Pass System

    Article • The Scientific World JOURNAL, January 2014, Hindawi Publishing Corporation

    Prof Sangjin Byun

  6. 1–5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector

    Article • IET Circuits Devices & Systems, May 2013, the Institution of Engineering and Technology (the IET)

    Prof Sangjin Byun

  7. Simple odd number frequency divider with 50% duty cycle

    Article • IEICE Electronics Express, January 2012, Institute of Electronics, Information and Communications Engineers (IEICE)

    Prof Sangjin Byun

  8. A low-power/high-resolution dual-mode analog-to-digital converter for wireless sensor applications

    Article • IEICE Electronics Express, January 2011, Institute of Electronics, Information and Communications Engineers (IEICE)

    Prof Sangjin Byun

  9. Charge Pump circuit with wide range digital leakage current mismatch compensator

    Article • IEICE Electronics Express, January 2010, Institute of Electronics, Information and Communications Engineers (IEICE)

    Prof Sangjin Byun

  10. A self-calibrated LC quadrature VCO in a current-limited region

    Article • June 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Prof Sangjin Byun

  11. A 600MHz CMOS OFDM LINC transmitter with a 7 bit digital phase modulator

    Article • June 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Prof Sangjin Byun

  12. A 20 Gb/s 1:4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 $\mu{\hbox {m}}$ CMOS Technology

    Article • IEEE Journal of Solid-State Circuits, January 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Prof Sangjin Byun

  13. A low-power 10-Gb/s 0.13-μm CMOS transmitter for OC-192/STM-64 applications

    Article • August 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Prof Sangjin Byun

  14. A 20gb/s 1:4 DEMUX without inductors in 0.13/spl mu/m CMOS

    Article • January 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Prof Sangjin Byun

  15. A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector

    Article • January 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Prof Sangjin Byun

  16. A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

    Article • IEEE Journal of Solid-State Circuits, February 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Prof Sangjin Byun

  17. A low-power cmos bluetooth rf transceiver with a digital offset canceling dll-based gfsk demodulator

    Article • IEEE Journal of Solid-State Circuits, October 2003, Institute of Electrical & Electronics Engineers (IEEE)

    Prof Sangjin Byun

  18. A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18 μm CMOS

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof Sangjin Byun