All Stories

  1. Impact of EUV patterning scenario on different design styles and their ground rules for 7nm/5nm node BEOL layers

    Article • March 2016, SPIE

    Dr Tsann-Bim Chiou

  2. Lithographic challenges and their solutions for critical layers in sub-14nm node logic devices

    Article • April 2013, SPIE

    Dr Tsann-Bim Chiou

  3. Impacts of overlay correction model and metrology sampling scheme on device yield

    Article • March 2012, SPIE

    Dr Tsann-Bim Chiou

  4. Improvement of lithography process by using a FlexRay illuminator for memory applications

    Article • March 2011, SPIE

    Dr Tsann-Bim Chiou

  5. Optimization of alignment/overlay sampling and marker layout to improve overlay performance for double patterning technology

    Article • December 2009, SPIE

    Dr Tsann-Bim Chiou

  6. Litho scenario solutions for FinFET SRAM 22nm node

    Article • December 2009, SPIE

    Dr Tsann-Bim Chiou

  7. Using intrafield high-order correction to achieve overlay requirement beyond sub-40nm node

    Article • March 2009, SPIE

    Dr Tsann-Bim Chiou

  8. Full-chip pitch/pattern splitting for lithography and spacer double patterning technologies

    Article • November 2008, SPIE

    Dr Tsann-Bim Chiou

  9. Development of layout split algorithms and printability evaluation for double patterning technology

    Article • March 2008, SPIE

    Dr Tsann-Bim Chiou

  10. How to obtain accurate resist simulations in very low-k1 era?

    Article • March 2006, SPIE

    Dr Tsann-Bim Chiou

  11. Double dipole lithography for 65-nm node and beyond: a technology readiness review

    Article • August 2004, SPIE

    Dr Tsann-Bim Chiou

  12. The Magnitude of Potential Exposure-Tool-Induced Critical Dimension and Overlay Errors in Double Dipole Lithography for the 65-nm and 45-nm Technology Nodes

    Article • Japanese Journal of Applied Physics, June 2004, Japan Society of Applied Physics

    Dr Tsann-Bim Chiou

  13. Experimental verification of a model-based decomposition method for double dipole lithography

    Article • May 2004, SPIE

    Dr Tsann-Bim Chiou

  14. 65-nm full-chip implementation using double dipole lithography

    Article • June 2003, SPIE

    Dr Tsann-Bim Chiou

  15. New methods to calibrate simulation parameters for chemically amplified resists

    Article • July 2002, SPIE

    Dr Tsann-Bim Chiou

  16. Calibration of ESCAP resist simulation parameters from consideration of printed CD pitch bias, CD measurement offset and wafer thermal history

    Article • July 2002, SPIE

    Dr Tsann-Bim Chiou

  17. Expanding the Process Window and Reducing the Optical Proximity Effect by Post-Exposure Delay

    Article • Journal of The Electrochemical Society, January 2001, The Electrochemical Society

    Dr Tsann-Bim Chiou

  18. New overlay pattern design for real-time focus and tilt monitor

    Article • August 2000, SPIE

    Dr Tsann-Bim Chiou

  19. Evaluation of fine pattern definition with electron-beam direct writing lithography

    Article • July 2000, SPIE

    Dr Tsann-Bim Chiou

  20. Postexposure Delay Effect on Linewidth Variation in Base Added Chemically Amplified Resist

    Article • Journal of The Electrochemical Society, January 2000, The Electrochemical Society

    Dr Tsann-Bim Chiou

  21. The magnitude of potential exposure tool induced CD and OL errors in the double exposure dipole (DDL) for 65 nm and 45 nm technology nodes

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Dr Tsann-Bim Chiou