Current affiliation: University of Technology SydneySubject: Electrical EngineeringPrimary location: Australia
Published in:IET Control Theory and ApplicationsPublication date:2016-07-18
This paper designs a robust discrete-time SMC for the systems involving packet losses in the actuation and measurement communication channels.
Published in:International Journal of ControlPublication date:2017-07-14
Published in:International Journal of Robust and Nonlinear ControlPublication date:2018-02-12