All Stories

  1. Low-Cost, Efficient Output-Only Infrastructure Damage Detection With Wireless Sensor Networks

    Article • IEEE Transactions on Systems Man and Cybernetics Systems, March 2020, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  2. Vector Coprocessor Virtualization for Simultaneous Multithreading

    Article • ACM Transactions on Embedded Computing Systems, May 2016, ACM (Association for Computing Machinery)

    Professor Sotirios Ziavras

  3. Wireless sensor networks for monitoring infrastructure

    Article • IET Wireless Sensor Systems, February 2016, the Institution of Engineering and Technology (the IET)

    Professor Sotirios Ziavras

  4. A Method to Measure Packet Processing Time of Hosts Using High-Speed Transmission Lines

    Article • IEEE Systems Journal, December 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  5. Instruction Fusion for Multiscalar and Many-Core Processors

    Article • International Journal of Parallel Programming, September 2015, Springer Science + Business Media

    Professor Sotirios Ziavras

  6. Modular vector processor architecture targeting at data-level parallelism

    Article • Microprocessors and Microsystems, June 2015, Elsevier

    Professor Sotirios Ziavras

  7. Performance-Energy Optimizations for Shared Vector Accelerators in Multicores

    Article • IEEE Transactions on Computers, March 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  8. A multiprocessor-on-a-programmable-chip reconfigurable system for matrix operations with power-grid case studies

    Article • International Journal of Computational Science and Engineering, January 2015, Inderscience Publishers

    Professor Sotirios Ziavras

  9. ASIC Design of Shared Vector Accelerators for Multicore Processors

    Article • October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  10. Message from CSE2013 Chairs

    Article • December 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  11. Efficient on-chip vector processing for multicore processors

    Article • October 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  12. Multicore-based vector coprocessor sharing for performance and energy gains

    Article • ACM Transactions on Embedded Computing Systems, September 2013, ACM (Association for Computing Machinery)

    Professor Sotirios Ziavras

  13. Packet classification using rule caching

    Article • July 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  14. FPGA and ASIC square root designs for high performance and power efficiency

    Article • June 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  15. Message from General Chairs - Volume I

    Article • November 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  16. Message from General Chairs - Volume II

    Article • November 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  17. Efficient face recognition using frequency distribution curve matching

    Article • IET Image Processing, November 2012, the Institution of Engineering and Technology (the IET)

    Professor Sotirios Ziavras

  18. Versatile design of shared vector coprocessors for multicores

    Article • Microprocessors and Microsystems, October 2012, Elsevier

    Professor Sotirios Ziavras

  19. Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, April 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  20. Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures

    Article • IET Computers & Digital Techniques, January 2012, the Institution of Engineering and Technology (the IET)

    Professor Sotirios Ziavras

  21. On-chip Vector Coprocessor Sharing for Multicores

    Article • February 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  22. Efficient packet classification on FPGAs also targeting at manageable memory consumption

    Article • December 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  23. Message from the General Chairs - CSE 2010

    Article • December 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  24. Efficient hardware support for pattern matching in network intrusion detection

    Article • Computers & Security, October 2010, Elsevier

    Professor Sotirios Ziavras

  25. Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm

    Article • Journal of Signal Processing Systems, September 2010, Springer Science + Business Media

    Professor Sotirios Ziavras

  26. Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance

    Article • September 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  27. Online Anonymity Protection in Computer-Mediated Communication

    Article • IEEE Transactions on Information Forensics and Security, September 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  28. PREFACE

    Article • International Journal on Artificial Intelligence Tools, August 2010, World Scientific Pub Co Pte Lt

    Professor Sotirios Ziavras

  29. TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array

    Article • July 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  30. Scheduling for input-queued packet switches by a re-configurable parallel match evaluator

    Article • IEEE Communications Letters, April 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  31. Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm

    Article • February 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  32. FPGA-based static analysis tool for detecting malicious binaries

    Article • February 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  33. Novel FPGA-Based Signature Matching for Deep Packet Inspection

    Article • January 2010, Springer Science + Business Media

    Professor Sotirios Ziavras

  34. Preventing Unwanted Social Inferences with Classification Tree Analysis

    Article • November 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  35. Message from the Program Chair

    Article • November 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  36. On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors

    Article • IEEE Transactions on Computers, September 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  37. Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches

    Article • August 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  38. On the Exploitation of Narrow-Width Values for Improving Register File Reliability

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, July 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  39. Exploiting narrow-width values for thermal-aware register file designs

    Article • April 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  40. Low-power multiplierless DCT for image/video coders

    Article • January 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  41. Social Inference Risk Modeling in Mobile and Social Applications

    Article • January 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  42. Designing for different levels of social inference risk

    Article • January 2009, ACM (Association for Computing Machinery)

    Professor Sotirios Ziavras

  43. Identity Inference as a Privacy Risk in Computer-Mediated Communication

    Article • January 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  44. Self-Adaptive Data Caches for Soft-Error Reliability

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  45. Asymmetrically banked value-aware register files for low-energy and high-performance

    Article • Microprocessors and Microsystems, May 2008, Elsevier

    Professor Sotirios Ziavras

  46. Concatenating Packets in Variable-Length Input-Queued Packet Switches with Cell-Based and Packet-Based Scheduling

    Article • April 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  47. BTB Access Filtering: A Low Energy and High Performance Design

    Article • January 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  48. Partially Reconfigurable Vector Processor for Embedded Applications

    Article • Journal of Computers, November 2007, International Academy Publishing (IAP)

    Professor Sotirios Ziavras

  49. Resource management for dynamically-challenged reconfigurable systems

    Article • September 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  50. Robust scalability analysis and SPM case studies

    Article • The Journal of Supercomputing, June 2007, Springer Science + Business Media

    Professor Sotirios Ziavras

  51. A Study of Data Exchange Protocols for the Grid Computing Environment

    Article • June 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  52. Measuring Network Parameters with Hardware Support

    Article • June 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  53. Parallel solution of Newton’s power flow equations on configurable chips

    Article • International Journal of Electrical Power & Energy Systems, June 2007, Elsevier

    Professor Sotirios Ziavras

  54. Runtime Partial Reconfiguration for Embedded Vector Processors

    Article • April 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  55. Coprocessor design to support MPI primitives in configurable multiprocessors

    Article • Integration, April 2007, Elsevier

    Professor Sotirios Ziavras

  56. FPGA-based Vector Processing for Matrix Operations

    Article • April 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  57. Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors

    Article • March 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  58. Reconfiguration support for vector operations

    Article • International Journal of High Performance Systems Architecture, January 2007, Inderscience Publishers

    Professor Sotirios Ziavras

  59. Vector Processing Support for FPGA-Oriented High Performance Applications

    Article • January 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  60. Asymmetrically Banked Value-Aware Register Files

    Article • January 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  61. System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors

    Article • October 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  62. On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors

    Article • July 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  63. A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers

    Article • IEICE Transactions on Information and Systems, February 2006, Institute of Electronics, Information and Communications Engineers (IEICE)

    Professor Sotirios Ziavras

  64. Exploiting mixed-mode parallelism for matrix operations on the HERA architecture through reconfiguration

    Article • IEE Proceedings - Computers and Digital Techniques, January 2006, the Institution of Engineering and Technology (the IET)

    Professor Sotirios Ziavras

  65. Message from the PEN-PCGCS Workshop Co-chairs

    Article • January 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  66. Modeling distributed data representation and its effect on parallel data accesses

    Article • Journal of Parallel and Distributed Computing, October 2005, Elsevier

    Professor Sotirios Ziavras

  67. Load-balanced CICB packet switch with support for long round-trip times

    Article • January 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  68. An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method

    Article • January 2005, Springer Science + Business Media

    Professor Sotirios Ziavras

  69. FPGA implementation of a Cholesky algorithm for a shared-memory multiprocessor architecture

    Article • Parallel Algorithms and Applications, December 2004, Taylor & Francis

    Professor Sotirios Ziavras

  70. A super-programming approach for mining association rules in parallel on PC clusters

    Article • IEEE Transactions on Parallel and Distributed Systems, September 2004, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  71. Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines

    Article • Concurrency and Computation Practice and Experience, February 2004, Wiley

    Professor Sotirios Ziavras

  72. PowerGrid - A Computation Engine for Large-Scale Electric Networks

    Article • December 2003, Office of Scientific and Technical Information (OSTI)

    Professor Sotirios Ziavras

  73. Processor design based on dataflow concurrency

    Article • Microprocessors and Microsystems, May 2003, Elsevier

    Professor Sotirios Ziavras

  74. Viable Architectures for High-Performance Computing

    Article • The Computer Journal, January 2003, Oxford University Press (OUP)

    Professor Sotirios Ziavras

  75. Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs)

    Article • Microprocessors and Microsystems, August 2002, Elsevier

    Professor Sotirios Ziavras

  76. INVESTIGATION OF A LOW-COST HIGH-PERFORMANCE SHARED-MEMORY MULTIPROCESSOR SYSTEM FOR REAL-TIME APPLICATIONS

    Article • August 2001, World Scientific Pub Co Pte Lt

    Professor Sotirios Ziavras

  77. A Universal, Dynamically Adaptable and Programmable Network Router for Parallel Computers

    Article • VLSI Design, January 2001, Hindawi Publishing Corporation

    Professor Sotirios Ziavras

  78. A new-generation parallel computer and its performance evaluation

    Article • Future Generation Computer Systems, November 2000, Elsevier

    Professor Sotirios Ziavras

  79. Evaluating the communications capabilities of the generalized hypercube interconnection network

    Article • Concurrency Practice and Experience, May 1999, Wiley

    Professor Sotirios Ziavras

  80. Investigation of Various Mesh Architectures With Broadcast Buses for High-Performance Computing

    Article • VLSI Design, January 1999, Hindawi Publishing Corporation

    Professor Sotirios Ziavras

  81. Material identification algorithms for parallel systems

    Article • Computers & Electrical Engineering, September 1996, Elsevier

    Professor Sotirios Ziavras

  82. Parallel DSP algorithms on TurboNet: an experimental system with hybrid message‐passing/shared‐memory architecture

    Article • Concurrency Practice and Experience, June 1996, Wiley

    Professor Sotirios Ziavras

  83. Parallel DSP algorithms on TurboNet: an experimental system with hybrid message-passing/shared-memory architecture

    Article • Concurrency Practice and Experience, June 1996, Wiley

    Professor Sotirios Ziavras

  84. Data broadcasting and reduction, prefix computation, and sorting on reduced hypercube parallel computers

    Article • Parallel Computing, June 1996, Elsevier

    Professor Sotirios Ziavras

  85. FACILITATING HIGH-PERFORMANCE IMAGE ANALYSIS ON REDUCED HYPERCUBE (RH) PARALLEL COMPUTERS

    Article • December 1995, World Scientific Pub Co Pte Lt

    Professor Sotirios Ziavras

  86. FACILITATING HIGH-PERFORMANCE IMAGE ANALYSIS ON REDUCED HYPERCUBE (RH) PARALLEL COMPUTERS

    Article • International Journal of Pattern Recognition and Artificial Intelligence, August 1995, World Scientific Pub Co Pte Lt

    Professor Sotirios Ziavras

  87. SCALABLE MULTIFOLDED HYPERCUBES FOR VERSATILE PARALLEL COMPUTERS

    Article • Parallel Processing Letters, June 1995, World Scientific Pub Co Pte Lt

    Professor Sotirios Ziavras

  88. Adaptive Multiresolution Structures for Image Processing on Parallel Computers

    Article • Journal of Parallel and Distributed Computing, December 1994, Elsevier

    Professor Sotirios Ziavras

  89. High-performance emulation of hierarchical structures on hypercube supercomputers

    Article • Concurrency Practice and Experience, April 1994, Wiley

    Professor Sotirios Ziavras

  90. RH: a versatile family of reduced hypercube interconnection networks

    Article • IEEE Transactions on Parallel and Distributed Systems, January 1994, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  91. Binary trees of modified hypercubes: a family of networks for hypercube-like parallel computers

    Article • International Journal of Electronics, January 1994, Taylor & Francis

    Professor Sotirios Ziavras

  92. Processor allocation strategies for modified hypercubes

    Article • IEE Proceedings - Computers and Digital Techniques, January 1994, the Institution of Engineering and Technology (the IET)

    Professor Sotirios Ziavras

  93. Connected component labelling on the BLITZEN massively parallel processor

    Article • Image and Vision Computing, December 1993, Elsevier

    Professor Sotirios Ziavras

  94. Pyramid mappings onto hypercubes for computer vision: Connection machine comparative study

    Article • Concurrency Practice and Experience, September 1993, Wiley

    Professor Sotirios Ziavras

  95. Mapping single and multiple multilevel structures onto the hypercube

    Article • IEE Proceedings E Computers and Digital Techniques, January 1993, the Institution of Engineering and Technology (the IET)

    Professor Sotirios Ziavras

  96. Efficient mapping algorithms for a class of hierarchical systems

    Article • IEEE Transactions on Parallel and Distributed Systems, January 1993, Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  97. On the problem of expanding hypercube-based systems

    Article • Journal of Parallel and Distributed Computing, September 1992, Elsevier

    Professor Sotirios Ziavras

  98. Connection Machine results for pyramid embedding algorithms

    Article • January 1992, Springer Science + Business Media

    Professor Sotirios Ziavras

  99. On the mapping problem for multi-level systems

    Article • January 1989, ACM (Association for Computing Machinery)

    Professor Sotirios Ziavras

  100. Improved algorithms for translation of pictures represented by leaf codes

    Article • Image and Vision Computing, February 1988, Elsevier

    Professor Sotirios Ziavras

  101. In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  102. Adaptive Scheduling of Array-Intensive Applications on Mixed-Mode Reconfigurable Multiprocessors

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  103. Load balancing on PC clusters with the super-programming model

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  104. Load balancing on PC clusters with the super-programming model

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  105. H-SIMD machine: configurable parallel computing for matrix multiplication

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  106. A configurable mu ltiprocessor and dynamic load balancing for parallel LU factorization

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  107. Performance optimization of an FPGA-based configurable multiprocessor for matrix operations

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  108. Optimizing the thermal behavior of subarrayed data caches

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  109. Versatile processor design for efficiency and high performance

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  110. A framework for dynamic resource assignment and scheduling on reconfigurable mixed-mode on-chip multiprocessors

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  111. Parallel direct solution of linear equations on FPGA-based machines

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  112. A class of scalable architectures for high-performance, cost-effective parallel computing

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  113. A low-complexity parallel system for gracious scalable performance. Case study for near PetaFLOPS computing

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  114. Powerful and feasible processor interconnections with an evaluation of their communications capabilities

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  115. High performance mapping for massively parallel hierarchical structures

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  116. Embedding multilevel structures into massively parallel hypercubes-connection machine results for computer vision algorithms

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  117. Performance analysis for an important class of parallel-processing networks

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  118. A defect identification algorithm for sequential and parallel computers

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  119. Processor allocation for a class of hypercube-like supercomputers

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  120. Efficient implementation of multilevel algorithms on hypercube supercomputers for computer vision

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  121. A hierarchically-controlled simd machine for 2D DCT on FPGAs

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras

  122. FPGA-Based Vector Processing for Solving Sparse Sets of Equations

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Professor Sotirios Ziavras