All Stories

  1. Acceleration of DNN Backward Propagation by Selective Computation of Gradients
  2. Tapered-Ratio Compression for Residual Network
  3. Benzene
  4. A new stochastic mutiplier for deep neural networks
  5. Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch
  6. Reconfigurable Architectures
  7. AIM
  8. PIM-enabled instructions
  9. A scalable processing-in-memory accelerator for parallel graph processing
  10. Arbitration in NoC for Equality of Service
  11. Reconfigurable Architectures
  12. Approximate de-randomizer for stochastic circuits
  13. REDELF
  14. A scalable processing-in-memory accelerator for parallel graph processing
  15. PIM-enabled instructions
  16. Concept-aware ensemble system for pedestrian detection
  17. Critical-path-aware high-level synthesis with distributed controller for fast timing closure
  18. Deflection routing in 3D network-on-chip with limited vertical bandwidth
  19. Fast custom instruction generation under area constraint
  20. SAT-based state encoding for peak current Minimization
  21. Multi-codec variable length decoder design with configurable processor
  22. Mapping control intensive kernels onto coarse-grained reconfigurable array architecture
  23. Modeling functional unit delays for bit-level chaining
  24. Configurable processors for embedded computing
  25. Performance-driven scheduling with bit-level chaining
  26. Rate assignment for embedded reactive real-time systems
  27. Power-conscious High Level Synthesis Using Loop Folding
  28. Software synthesis through task decomposition by dependency analysis
  29. Loop pipelining in hardware-software partitioning
  30. Narrow bus encoding for low power systems