All Stories

  1. DeMiST: Detection and Mitigation of Stealthy Analog Hardware Trojans
  2. Enhancing the Security of Collaborative Deep Neural Networks: An Examination of the Effect of Low Pass Filters
  3. LaBaNI: Layer-based Noise Injection Attack on Convolutional Neural Networks
  4. InTrust-IoT: Intelligent Ecosystem based on Power Profiling of Trusted device(s) in IoT for Hardware Trojan Detection
  5. Grouped through silicon vias for lower Ldi/dt drop in three-dimensional integrated circuit
  6. Tenacious hardware trojans due to high temperature in middle tiers of 3-D ICs
  7. Hardware Trojans in asynchronous FIFO-buffers: From clock domain crossing perspective
  8. Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits
  9. Hardware Trojan detection in soft error tolerant macro synchronous micro asynchronous (MSMA) pipeline
  10. Modeling, analyzing, and abstracting single event transient propagation at gate level
  11. New Insights Into the Single Event Transient Propagation Through Static and TSPC Logic
  12. Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline
  13. Introducing redundant TSV with low inductance for 3-D IC
  14. Abstracting Single Event Transient characteristics variations due to input patterns and fan-out
  15. Timing variation aware dynamic digital phase detector for low-latency clock domain crossing
  16. Investigating the impact of propagation paths and re-convergent paths on the propagation induced pulse broadening
  17. Soft error aware pipelined architecture: Leveraging automatic repeat request protocol
  18. Design of a C-element based clock domain crossing interface
  19. Towards low area overhead ARQ based soft error tolerant data paths for SRAM-based Altera FPGAs
  20. Identification of soft error glitch-propagation paths: Leveraging SAT solvers
  21. A novel hybrid FIFO asynchronous clock domain crossing interfacing method
  22. SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level
  23. All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs
  24. Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems
  25. An all-digital skew-adaptive clock scheduling algorithm for heterogeneous multiprocessor systems on chips (MPSoCs)
  26. All-digital skew-tolerant interfacing method for systems with rational frequency ratios among Multiple Clock Domains: Leveraging a priori timing information
  27. Metastability tolerant mesochronous synchronization
  28. Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology
  29. Optimal partitioning of globally asychronous locally synchronous processor arrays