All Stories

  1. Time interval generator with 8 ps resolution and wide range for large TDC array characterization

    Article • Analog Integrated Circuits and Signal Processing, October 2015, Springer Science + Business Media

    Dr Ion Vornicu

  2. Compact CMOS active quenching/recharge circuit for SPAD arrays

    Article • International Journal of Circuit Theory and Applications, July 2015, Wiley

    Dr Ion Vornicu

  3. On the calibration of a SPAD-based 3D imager with in-pixel TDC using a time-gated technique

    Article • May 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Ion Vornicu

  4. A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measurement

    Article • March 2015, SPIE

    Dr Ion Vornicu

  5. On-chip time-of-flight estimation in standard CMOS technology

    Article • SPIE Newsroom, February 2015, SPIE

    Dr Ion Vornicu

  6. Wide range 8ps incremental resolution time interval generator based on FPGA technology

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Ion Vornicu

  7. A CMOS 0.18μm 64×64 single photon image sensor with in-pixel 11b time-to-digital converter

    Article • October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Ion Vornicu

  8. A CMOS 8×8 SPAD array for Time-of-Flight measurement and light-spot statistics

    Article • May 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Ion Vornicu

  9. On the possibilities of using a class of CNN's for texture classification

    Article • August 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Ion Vornicu

  10. On the design of a class of CNN's for ECG classification

    Article • August 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Ion Vornicu

  11. Image processing using a CMOS analog parallel architecture

    Article • October 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Ion Vornicu

  12. Log-domain CMOS implementation of a class of analog parallel architectures

    Article • October 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Ion Vornicu

  13. Spatial filtering using linear analog parallel architectures

    Article • July 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Ion Vornicu