All Stories

  1. Process compensated BJT-based CMOS temperature sensor with a ±1.5 °C (3σ) batch-to-batch inaccuracy
  2. Exploring the behavior of water nanodroplet on a coplanar electrowetting-on-dielectric: A molecular dynamics approach
  3. Improving the Linearity and Power Efficiency of Active Switched-Capacitor Filters in a Compact Die Area
  4. Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques
  5. A 0.02 mm$^{2}$ 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad
  6. A 0.07 mm$^{2}$ 2.2 mW 10 GHz Current-Reuse Class-B/C Hybrid VCO Achieving 196-dBc/Hz FoM$_{{\rm A}}$
  7. A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links
  8. A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth
  9. 0.0045 mm2 15.8 µW three-stage amplifier driving 10×-wide (0.15–1.5 nF) capacitive loads with >50° phase margin
  10. A 0.0045- $\hbox{mm}^{2}$ 32.4- $\mu\hbox{W} $ Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensa...
  11. 2.4 A 0.028mm2 11mW single-mixing blocker-tolerant receiver with double-RF N-path filtering, S11 centering, +13dBm OB-IIP3 and 1.5-to-2.9dB NF
  12. Adhesion promoter for a multi-dielectric-layer on a digital microfluidic chip
  13. NMR meets microfluidics
  14. Wideband Receivers: Design Challenges, Tradeoffs and State-of-the-Art
  15. A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tolerant capacitive sensor readout
  16. A 0.002-mm$^{2}$ 6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver With 59.6% Horizontal Eye Opening Under 23.3-dB Channel Loss at Nyquist Frequency
  17. A Sub-GHz Multi-ISM-Band ZigBee Receiver Using Function-Reuse and Gain-Boosted N-Path Techniques for IoT Applications
  18. A 104μW EMI-resisting bandgap voltage reference achieving −20dB PSRR, and 5% DC shift under a 4dBm EMI level
  19. Design considerations of a low-noise receiver front-end and its spiral coil for portable NMR screening
  20. An RF-to-BB-Current-Reuse Wideband Receiver With Parallel N-Path Active/Passive Mixers and a Single-MOS Pole-Zero LPF
  21. Muscle and electrode motion artifacts reduction in ECG using adaptive Fourier decomposition
  22. A 0.137 mm$^{{2}}$ 9 GHz Hybrid Class-B/C QVCO With Output Buffering in 65 nm CMOS
  23. Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter
  24. On the droplet velocity and electrode lifetime of digital microfluidics: voltage actuation techniques and comparison
  25. A 0.14-${\hbox {mm}}^{2}$ 1.4-mW 59.4-dB-SFDR 2.4-GHz ZigBee/WPAN Receiver Exploiting a “Split-LNTA + 50% LO” Topology in 65-nm CMOS
  26. Micropower two-stage amplifier employing recycling current-buffer Miller compensation
  27. A 26.3 dBm 2.5 to 6 GHz wideband class-D switched-capacitor power amplifier with 40% peak PAE
  28. A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS
  29. Natural discharge after pulse and cooperative electrodes to enhance droplet velocity in digital microfluidics
  30. A sine-LO square-law harmonic-rejection mixer—theory, implementation, and application
  31. 17.2 A 0.0013mm2 3.6μW nested-current-mirror single-stage amplifier driving 0.15-to-15nF capacitive loads with >62° phase margin
  32. 9.4 A 0.5V 1.15mW 0.2mm2 Sub-GHz ZigBee receiver supporting 433/860/915/960MHz ISM bands with zero external components
  33. 3.9 An RF-to-BB current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF
  34. NMR–DMF: a modular nuclear magnetic resonance–digital microfluidics system for biological assays
  35. A 0.127-mm2, 5.6-mW, 5th-order SC LPF with +23.5-dBm IIP3 and 1.5-to-15-MHz clock-defined bandwidth in 65-nm CMOS
  36. A Single-Branch Third-Order Pole–Zero Low-Pass Filter With 0.014- $\hbox{mm}^{2}$ Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth–Power Scalability
  37. 0.013 mm2, kHz-to-GHz-bandwidth, third-order all-pole lowpass filter with 0.52-to-1.11 pW/pole/Hz efficiency
  38. 15-nW Biopotential LPFs in 0.35- $\mu{\rm m}$ CMOS Using Subthreshold-Source-Follower Biquads With and Without Gain Compensation
  39. Systematic analysis and cancellation of kickback noise in a dynamic latched comparator
  40. A 53-to-75-mW, 59.3-dB HRR, TV-Band White-Space Transmitter Using a Low-Frequency Reference LO in 65-nm CMOS
  41. A wideband multi-stage inverter-based driver amplifier for IEEE 802.22 WRAN transmitters
  42. A 2.93μW 8-bit capacitance-to-RF converter for movable laboratory mice blood pressure monitoring
  43. A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware
  44. Sub-threshold standard cell library design for ultra-low power biomedical applications
  45. A 3.6-mW 6-GHz current-reuse VCO-buffer with improved load drivability in 65-nm CMOS
  46. Optimization of microwatt on-chip charge pump for single-chip solar energy harvesting
  47. An ultra-low power CMOS smart temperature sensor for clinical temperature monitoring
  48. Standard cell library design with voltage scaling and transistor sizing for ultra-low-power biomedical applications
  49. Correction to "A 0.016 mm² 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With >0.95-MHz GBW"
  50. 0.0012 mm2, 8 mW, single-to-differential converter with < 1.1% data cross error and < 3.4 ps RMS jitter up to 14 Gbit/s data rate
  51. A 1.83 μW, 0.78 μVrms input referred noise neural recording front end
  52. A 0.5V 10GHz 8-phase LC-VCO Combining current-reuse and back-gate-coupling techniques consuming 2mW
  53. A 1.7mW 0.22mm2 2.4GHz ZigBee RX exploiting a current-reuse blixer + hybrid filter topology in 65nm CMOS
  54. A 0.016-mm$^{2}$ 144-$\mu$ W Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With
  55. An intelligent digital microfluidic system with fuzzy-enhanced feedback for multi-droplet manipulation
  56. Construction of a microfluidic chip, using dried-down reagents, for LATE-PCR amplification and detection of single-stranded DNA
  57. Canonical Correlation Analysis Neural Network for Steady-State Visual Evoked Potentials Based Brain-Computer Interfaces
  58. A Fifth-Order 20-MHz Transistorized-$LC$ -Ladder LPF With 58.2-dB SFDR, 68-$\mu\hbox{W/Pole/MHz}$ Efficiency, and 0.13-<...
  59. A dynamic-range-improved 2.4GHz WLAN class-E PA combining PWPM and cascode modulation
  60. A 0.83-$\mu {\rm W}$ QRS Detection Processor Using Quadratic Spline Wavelet Transform for Wireless ECG Acquisition in 0.35- $\mu{\rm m}$...
  61. A 0.8 µW 8-bit 1.5∼20-pF-input-range capacitance-to-digital converter for lab-on-chip digital microfluidics systems
  62. Individual alpha neurofeedback training effect on short term memory
  63. Enhanced RFICs in Nanoscale CMOS
  64. Flashing color on the performance of SSVEP-based brain-computer interfaces
  65. Implementation of SSVEP based BCI with Emotiv EPOC
  66. Neurofeedback for the treatment of schizophrenia: Case study
  67. A Further Study on Short Term Memory Improvement by Neurofeedback
  68. A 0.02-to-6GHz SDR balun-LNA using a triple-stage inverter-based amplifier
  69. A Wearable Wireless General Purpose Bio-signal Acquisition Prototype System for Home Healthcare
  70. A frequency-translation technique for low-noise ultra-low-cutoff lowpass filtering
  71. A 0.016mm2 144μW three-stage amplifier capable of driving 1-to-15nF capacitive load with >0.95MHz GBW
  72. Interview
  73. High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS
  74. Conclusions
  75. Introduction
  76. Trial pruning based on genetic algorithm for single-trial EEG classification
  77. A Mixed-Voltage Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS
  78. A High-Voltage-Enabled Mobile-TV RF Front-End in 90-nm CMOS
  79. General Considerations of High-/Mixed-VDD Analog and RF Circuits and Systems
  80. A Full-Band Mobile-TV LNA with Mixed-Voltage ESD Protection in 90-nm CMOS
  81. Robust Learning of Mixture Models and Its Application on Trial Pruning for EEG Signal Analysis
  82. Object Recognition Test in Peripheral Vision: A Study on the Influence of Object Color, Pattern and Shape
  83. A real-time heart beat detector and quantitative investigation based on FPGA
  84. A double active-decoupling technique for reducing package effects in a cognitive-radio balun-LNA
  85. A novel digital predistortion technique for class-E PA with delay mismatch estimation
  86. A 0.46-mm$ ^{2}$ 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS
  87. Double recycling technique for folded-cascode OTA
  88. An ultra-low-power filtering technique for biomedical applications
  89. Entropy penalized learning for Gaussian mixture models
  90. A Solution to harmonic frequency problem: Frequency and phase coding-based brain-computer interface
  91. An online SSVEP-based chatting system
  92. A high-voltage-enabled recycling folded cascode OpAmp for nanoscale CMOS technologies
  93. A single-to-differential LNA topology with robust output gain-phase balancing against balun imbalance
  94. A high rate online SSVEP based brain-computer interface speller
  95. Outlier detection for single-trial EEG signal analysis
  96. A highly-linear ultra-wideband balun-LNA for cognitive radios
  97. A comparison of minimum energy combination and canonical correlation analysis for SSVEP detection
  98. Can Artificial Intelligence Be Realized, and Will it Benefit Humanity? [The Way I See it]
  99. A 0.46mm2 4dB-NF unified receiver front-end for full-band mobile TV in 65nm CMOS
  100. ECG heart beat detection via Mathematical Morphology and Quadratic Spline wavelet transform
  101. Two Stage Operational Amplifiers: Power and Area Efficient Frequency Compensation for Driving a Wide Range of Capacitive Load
  102. Gaussian mixture model based on genetic algorithm for brain-computer interface
  103. An improved phase-tagged stimuli generation method in steady-state visual evoked potential based brain-computer interface
  104. A 28-μW EEG readout front-end utilizing a current-mode instrumentation amplifier and a source-follower-based LPF
  105. A novel response-translating lowpass filter achieving 1.4-to-15-Hz tunable cutoff for biopotential acquisition systems
  106. Trial pruning for classification of single-trial EEG data during motor imagery
  107. A $2\times V_{\rm DD}$-Enabled Mobile-TV RF Front-End With TV-GSM Interoperability in 1-V 90-nm CMOS
  108. SC biquad filter with hybrid utilization of OpAmp and comparator-based circuit
  109. Source-follower-based bi-quad cell for continuous-time zero-pole type filters
  110. Analysis and Design of Open-Loop Multiphase Local-Oscillator Generator for Wireless Applications
  111. High-/Mixed-Voltage RF and Analog CMOS Circuits Come of Age
  112. Assisting the Career Development of Young Members—Examples of What IEEE CAS Society Have Recently Done [CAS Education
  113. EEG signals classification for brain computer interfaces based on Gaussian process classifier
  114. Starting a new team in microelectronics development---SWOT and new initiatives
  115. Design of current mode instrumentation amplifier for portable biosignal acquisition system
  116. An active-balun LNA with forestage-poststage gain controls for VHF/UHF mobile-TV tuners
  117. A 2.4 Hz-to-10 kHz-tunable biopotential filter using a novel capacitor multiplier
  118. Comparison of different classification methods for EEG-based brain computer interfaces: A case study
  119. An open-loop octave-phase local-oscillator generator with high-precision correlated phases for VHF/UHF mobile-TV tuners
  120. A 90nm CMOS bio-potential signal readout front-end with improved powerline interference rejection
  121. Design of an ESD-Protected Ultra-Wideband LNA in Nanoscale CMOS for Full-Band Mobile TV Tuners
  122. Explosive growth calls for more mixed-voltage analog integrated circuits
  123. Circuits and systems education: viewpoint of GOLD and industry
  124. A DC-offset-compensated, CT/DT hybrid filter with process-insensitive cutoff and low in-band group-delay variation for WLAN receivers
  125. An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners
  126. On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems
  127. A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC
  128. Analog-Baseband Architectures And Circuits For Multistandard And Lowvoltage Wireless Transceivers
  129. Transceiver architecture selection: Review, state-of-the-art survey and case study
  130. Two-step channel selection-a novel technique for reconfigurable multistandard transceiver front-ends
  131. Multistandard-compliant receiver architecture with low-voltage implementation
  132. Two-step channel selection technique by programmable digital-double quadrature sampling for complex low-IF receivers
  133. I/Q imbalance modeling of quadrature wireless transceiver analog front-ends in SIMULINK
  134. A programmable switched-capacitor A-DQS frequency downconverter for two-step channel selection wireless receiver
  135. A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications
  136. A novel IF channel selection technique by analog-double quadrature sampling for complex low-IF receivers
  137. A Frequency Up-Conversion and Two-Step Channel Selection Embedded CMOS D/A Interface
  138. Modeling of noise sources in reference voltage generator for very-high-speed pipelined ADC
  139. Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers
  140. Frequency-downconversion and IF channel selection A-DQS sample-and-hold pair for two-step-channel-select low-IF receiver
  141. A front-to-back-end modeling of I/Q mismatch effects in a complex-IF receiver for image-rejection enhancement
  142. An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver
  143. A 3D PWM control, H-bridge tri-level inverter for power quality compensation in three-phase four-wired systems
  144. A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-μm