All Stories

  1. A Study on Hyperparameters Configurations for an Efficient Human Activity Recognition System
  2. A methodology and framework for software memoization of functions
  3. Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey
  4. Compiler Techniques for Efficient MATLAB to OpenCL Code Generation
  5. Introduction to the Special Section on FPL 2015
  6. The First 25 Years of the FPL Conference
  7. Foreword to the special issue of the 18th IEEE international conference on computational science and engineering (CSE2015)
  8. SSA-based MATLAB-to-C compilation and optimization
  9. The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems
  10. A MATLAB subset to C compiler targeting embedded systems
  11. Clustering-Based Selection for the Exploration of Compiler Optimization Sequences
  12. Guest Editorial ARC 2014
  13. Techniques for efficient MATLAB-to-C compilation
  14. Guest Editorial FPL 2013
  15. C and OpenCL generation from MATLAB
  16. Transparent Acceleration of Program Execution using Reconfigurable Hardware
  17. Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach
  18. Enabling FPGA routing configuration sharing in dynamic partial reconfiguration
  19. Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support
  20. A clustering-based approach for exploring sequences of compiler optimizations
  21. Exploration of compiler optimization sequences using clustering-based selection
  22. High-Level Synthesis from C vs. a DSL-Based Approach
  23. Reconfigurable Computing: Architectures, Tools, and Applications
  24. Multi-Target C Code Generation from MATLAB
  25. Coarse/Fine-grained Approaches for Pipelining Computing Stages in FPGA-Based Multicore Architectures
  26. Exploration of compiler optimization sequences using clustering-based selection
  27. General chair message
  28. Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
  29. Enriching MATLAB with aspect-oriented features for developing embedded systems
  30. The MATISSE MATLAB compiler
  31. Related Work
  32. Introduction
  33. Compilation and Synthesis for Embedded Reconfigurable Systems
  34. The LARA Language
  35. Conclusions
  36. Architecture for Transparent Binary Acceleration of Loops with Memory Accesses
  37. Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units
  38. LARA Experiments
  39. An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits
  40. An FPGA-based multi-core approach for pipelining computing stages
  41. The REFLECT Design-Flow
  42. Resource-Efficient Designs Using an Aspect-Oriented Approach
  43. Controlling Hardware Synthesis with Aspects
  44. Hardware pipelining of runtime-detected loops
  45. Programming strategies for runtime adaptability
  46. Hardware/software specialization through aspects: The LARA approach
  47. Analysis of error detection schemes: Toolchain support and hardware/software implications
  48. Specifying Compiler Strategies for FPGA-based Systems
  49. LARA
  50. Program and Aspect Metrics for MATLAB
  51. Experiments with the LARA aspect-oriented approach
  52. From Instruction Traces to Specialized Reconfigurable Arrays
  53. Techniques for Dynamically Mapping Computations to Coprocessors
  54. Identifying Merge-Beneficial Software Kernels for Hardware Implementation
  55. LALP: A Language to Program Custom FPGA-Based Acceleration Engines
  56. A Domain-Specific Language for the Specification of Adaptable Context Inference
  57. Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks
  58. Programming safety requirements in the REFLECT design flow
  59. Reconfigurable Computing
  60. Conclusion
  61. Introduction
  62. Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)
  63. Code Transformations for Embedded Reconfigurable Computing Architectures
  64. REFLECT: Rendering FPGAs to Multi-core Embedded Computing
  65. On identifying and optimizing instruction sequences for dynamic compilation
  66. A Query Processing Strategy for Conceptual Queries Based on Object-Role Modeling
  67. On Identifying Segments of Traces for Dynamic Compilation
  68. On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates
  69. On using LALP to map an audio encoder/decoder on FPGAs
  70. Compiling for reconfigurable computing
  71. Providing user context for mobile and social networking applications
  72. Welcome message
  73. Preprocessing techniques for context recognition from accelerometer data
  74. Unbalanced FIFO sorting for FPGA-based systems
  75. A comparison of three representative hardware sorting units
  76. LALP: A Novel Language to Program Custom FPGA-Based Architectures
  77. Automatic generation of FPGA hardware accelerators using a domain specific language
  78. Compilation Techniques for Reconfigurable Architectures
  79. The current feasibility of gesture recognition for a smartphone using J2ME
  80. An Analysis of Navigation Algorithms for Smartphones Using J2ME
  81. Mobile Context Provider for Social Networking
  82. Synthesis of regular expressions for FPGAs
  83. IJE special issue on reconfigurable hardware systems
  84. Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures
  85. Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures
  86. Introduction
  87. Compilers for Reconfigurable Architectures
  88. Overview of Reconfigurable Architectures
  89. Final Remarks
  90. Code Transformations
  91. Compilation and Synthesis Flows
  92. Mapping and Execution Optimizations
  93. Perspectives on Programming Reconfigurable Computing Platforms
  94. Regular Expression Matching in Reconfigurable Hardware
  95. Aggressive Loop Pipelining for Reconfigurable Architectures
  96. An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics
  97. On Adapting Power Estimation Models for Embedded Soft-Core Processors
  98. A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops
  99. Reconfigurable Computing: Architectures, Tools and Applications
  100. A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures
  101. Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements
  102. A Methodology to Design FPGA-based PID Controllers
  103. Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures
  104. Reconfigurable Computing: Architectures and Applications
  105. New challenges in computer science education
  106. Dynamic loop pipelining in data-driven architectures
  107. New challenges in computer science education
  108. Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping
  109. Self-loop Pipelining and Reconfigurable Dataflow Arrays
  110. Modeling Loop Unrolling: Approaches and Open Issues
  111. An Environment for Exploring Data-Driven Architectures
  112. XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture
  113. Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
  114. An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs
  115. Architectures and compilers to support reconfigurable computing
  116. Compilation and Temporal Partitioning for a Coarse-grain Reconfigurable Architecture
  117. Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues
  118. The Role of Programming Models on Reconfigurable Computing Fabrics