All Stories

  1. A portable class of 3-transistor current references with low-power sub-0.5 V operation

    Article • International Journal of Circuit Theory and Applications, December 2017, Wiley

    Dr Marco Lanuzza

  2. Low energy/delay overhead level shifter for wide-range voltage conversion

    Article • International Journal of Circuit Theory and Applications, November 2016, Wiley

    Dr Marco Lanuzza

  3. Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, February 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  4. Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  5. Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

    Article • International Journal of Circuit Theory and Applications, August 2014, Wiley

    Dr Marco Lanuzza

  6. Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, May 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  7. Improving speed and power characteristics of pulse-triggered flip-flops

    Article • February 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  8. Dynamic gate-level body biasing for subthreshold digital design

    Article • February 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  9. A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops

    Article • Journal of Low Power Electronics, December 2013, American Scientific Publishers

    Dr Marco Lanuzza

  10. Designing Dynamic Carry Skip Adders: Analysis and Comparison

    Article • Circuits Systems and Signal Processing, October 2013, Springer Science + Business Media

    Dr Marco Lanuzza

  11. Design of high-speed low-power parallel-prefix adder trees in nanometer technologies

    Article • International Journal of Circuit Theory and Applications, January 2013, Wiley

    Dr Marco Lanuzza

  12. A Comparative Study of MWT Architectures by Means of Numerical Simulations

    Article • Energy Procedia, January 2013, Elsevier

    Dr Marco Lanuzza

  13. Low-Power Level Shifter for Multi-Supply Voltage Designs

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, December 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  14. Analyzing noise robustness of wide fan-in dynamic logic gates under process variations

    Article • International Journal of Circuit Theory and Applications, October 2012, Wiley

    Dr Marco Lanuzza

  15. Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates

    Article • International Journal of Circuit Theory and Applications, August 2012, Wiley

    Dr Marco Lanuzza

  16. Comparative analysis of yield optimized pulsed flip-flops

    Article • Microelectronics Reliability, August 2012, Elsevier

    Dr Marco Lanuzza

  17. Optimization of Rear Point Contact Geometry by Means of 3-D Numerical Simulation

    Article • Energy Procedia, January 2012, Elsevier

    Dr Marco Lanuzza

  18. Self-repairing SRAM architecture to mitigate the inter-die process variations at 65nm technology

    Article • May 2011, SPIE

    Dr Marco Lanuzza

  19. Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations

    Article • Journal of Low Power Electronics and Applications, April 2011, MDPI AG

    Dr Marco Lanuzza

  20. Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis

    Article • January 2011, Springer Science + Business Media

    Dr Marco Lanuzza

  21. Design and evaluation of high-speed energy-aware carry skip adders

    Article • December 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  22. Design Space Exploration of Split-Path Data Driven Dynamic Full Adder

    Article • Journal of Low Power Electronics, December 2010, American Scientific Publishers

    Dr Marco Lanuzza

  23. Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications

    Article • ACM Transactions on Reconfigurable Technology and Systems, December 2010, ACM (Association for Computing Machinery)

    Dr Marco Lanuzza

  24. Impact of Random Process Variations on Different 65nm SRAM Cell Topologies

    Article • November 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  25. Energy-efficient single-clock-cycle binary comparator

    Article • International Journal of Circuit Theory and Applications, July 2010, Wiley

    Dr Marco Lanuzza

  26. A self-hosting configuration management system to mitigate the impact of Radiation-Induced Multi-Bit Upsets in SRAM-based FPGAs

    Article • July 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  27. Impact of Process Variations on Flip-Flops Energy and Timing Characteristics

    Article • July 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  28. A new low-power high-speed single-clock-cycle binary comparator

    Article • May 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  29. A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder

    Article • January 2010, Springer Science + Business Media

    Dr Marco Lanuzza

  30. An Embedded System for EEG Acquisition and Processing for Brain Computer Interface Applications

    Article • January 2010, Springer Science + Business Media

    Dr Marco Lanuzza

  31. Low-power split-path data-driven dynamic logic

    Article • IET Circuits Devices & Systems, December 2009, the Institution of Engineering and Technology (the IET)

    Dr Marco Lanuzza

  32. Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems

    Article • Journal of Low Power Electronics, October 2009, American Scientific Publishers

    Dr Marco Lanuzza

  33. A novel ICA-based hardware system for reconfigurable and portable BCI

    Article • May 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  34. Designing High-Speed Adders in Power-Constrained Environments

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, February 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  35. Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath

    Article • January 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  36. New performance/power/area efficient, reliable full adder design

    Article • January 2009, ACM (Association for Computing Machinery)

    Dr Marco Lanuzza

  37. Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing

    Article • January 2009, Springer Science + Business Media

    Dr Marco Lanuzza

  38. An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

    Article • January 2009, Springer Science + Business Media

    Dr Marco Lanuzza

  39. Performance and reliability of ultra-thin oxide nMOSFETs under variable body bias

    Article • Microelectronic Engineering, September 2007, Elsevier

    Dr Marco Lanuzza

  40. A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications

    Article • August 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  41. Design and Implementation of a 90nm Low bit-rate Image Compression Core

    Article • August 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  42. Low bit rate image compression core for onboard space applications

    Article • IEEE Transactions on Circuits and Systems for Video Technology, January 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  43. A high-performance fully reconfigurable FPGA-based 2D convolution processor

    Article • Microprocessors and Microsystems, November 2005, Elsevier

    Dr Marco Lanuzza

  44. Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications

    Article • January 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  45. Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications

    Article • January 2005, ACM (Association for Computing Machinery)

    Dr Marco Lanuzza

  46. Variable precision arithmetic circuits for FPGA-based multimedia processors

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, September 2004, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  47. An efficient wavelet image encoder for FPGA-based designs

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  48. Low-cost fully reconfigurable data-path for FPGA-based multimedia processor

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Dr Marco Lanuzza

  49. MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing

    Article • Springer Science + Business Media

    Dr Marco Lanuzza