All Stories

  1. Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

    Article • Nanoscience &amp Nanotechnology-Asia, August 2020, Bentham Science Publishers

    Manash Chanda, DIPANJAN SEN

  2. Design and analysis of a logic model for ultra-low power near threshold adiabatic computing

    Article • IET Circuits Devices & Systems, February 2018, the Institution of Engineering and Technology (the IET)

    Manash Chanda

  3. Complete delay modeling of sub-threshold CMOS logic gates for low-power application

    Article • International Journal of Numerical Modelling Electronic Networks Devices and Fields, February 2015, Wiley

    Manash Chanda

  4. Modeling of parameters for nano-scale surrounding-gate MOSFET considering quantum mechanical effect

    Article • International Journal of Numerical Modelling Electronic Networks Devices and Fields, December 2013, Wiley

    Manash Chanda