All Stories

  1. Drain Side N+ Layout Manners ("npnpn" Arranged-Type) on ESD Robustness in the 60-V pLDMOS-SCR

    Article • Applied Mechanics and Materials, September 2017, Trans Tech Publications

    Prof. Shen-Li Chen

  2. A easy implementation for ESD strengthening about the HV LDMOS

    Article • Electronics Letters, September 2016, the Institution of Engineering and Technology (the IET)

    Prof. Shen-Li Chen

  3. Photoluminescence and Life-time Enhancements by the annealing process

    Article • The Open Materials Science Journal, July 2016, Bentham Science Publishers

    Prof. Shen-Li Chen

  4. Impacts of ESD Reliability by Different Layout Engineering in the 0.25-μm 60-V High-Voltage LDMOS Devices

    Article • Physical Sciences Reviews, April 2016, De Gruyter

    Prof. Shen-Li Chen

  5. ESD-Reliability Analysis and Strategy of the GaN-Based Light-Emitting Diodes

    Article • Key Engineering Materials, July 2015, Trans Tech Publications

    Prof. Shen-Li Chen

  6. Influences of MOS Device Characteristic under Different Oxygen-Dose Participations in the Silicon Substrate

    Article • Key Engineering Materials, July 2015, Trans Tech Publications

    Prof. Shen-Li Chen

  7. Reliability Enhancement in the 60 V Power pLDMOS by a Bulk-FOD Engineering

    Article • Advanced Materials Research, December 2014, Trans Tech Publications

    Prof. Shen-Li Chen