All Stories

  1. A Multi-objective Optimization Approach for the Capacitated Vehicle Routing Problem with Time Windows (CVRPTW)

    Article • January 2023, Springer Science + Business Media

    Prof. Haidar Harmanani

  2. A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules

    Article • International Journal of Computational Intelligence and Applications, June 2018, World Scientific Pub Co Pte Lt

    Prof. Haidar Harmanani

  3. Heuristic Approaches for the Open-Shop Scheduling Problem

    Article • January 2018, Springer Science + Business Media

    Prof. Haidar Harmanani

  4. Information Technology - New Generations

    Article • January 2018, Springer Science + Business Media

    Prof. Haidar Harmanani

  5. A Multiobjective Optimization Method for the SOC Test Time, TAM, and Power Optimization Using a Strength Pareto Evolutionary Algorithm

    Article • July 2017, Springer Science + Business Media

    Prof. Haidar Harmanani

  6. An outcome-based assessment process for accrediting computing programmes

    Article • European Journal of Engineering Education, August 2016, Taylor & Francis

    Prof. Haidar Harmanani

  7. A single switcher combined series parallel hybrid envelope tracking amplifier for wideband RF power amplifier applications

    Article • May 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  8. An all-digital fast tracking switching converter with a programmable order loop controller for envelope tracking RF power amplifiers

    Article • May 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  9. An enhanced light-load efficiency step down regulator with fine step frequency scaling

    Article • May 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  10. An Efficient Method for the Open-Shop Scheduling Problem Using Simulated Annealing

    Article • January 2016, Springer Science + Business Media

    Prof. Haidar Harmanani

  11. Key Edaphic Properties Largely Explain Temporal and Geographic Variation in Soil Microbial Communities across Four Biomes

    Article • PLoS ONE, November 2015, PLOS

    Prof. Haidar Harmanani

  12. An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components

    Article • August 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  13. A Parallel GPU Implementation of the Timber Wolf Placement Algorithm

    Article • April 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  14. Efficient shaped quantizer dithering implementation for sigma delta modulators

    Article • December 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  15. Thermal-aware test scheduling using network-on-chip under multiple clock rates

    Article • International Journal of Electronics, March 2013, Taylor & Francis

    Prof. Haidar Harmanani

  16. An effective solution to thermal-aware test scheduling on network-on-chip using multiple clock rates

    Article • August 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  17. A Stochastic Chartist–Fundamentalist Model with Time Delays

    Article • Computational Economics, June 2012, Springer Science + Business Media

    Prof. Haidar Harmanani

  18. Heuristic approaches for optimizing the performance of rule-based classifiers

    Article • August 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  19. An optimal formulation for test scheduling network-on-chip using multiple clock rates

    Article • May 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  20. Predicting stability of classes in an object-oriented system

    Article • Journal of Computational Methods in Sciences and Engineering, September 2010, IOS Press

    Prof. Haidar Harmanani

  21. A method for efficient NoC test scheduling using deterministic routing

    Article • September 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  22. Estimating test cost during data path and controller synthesis with low power overhead

    Article • May 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  23. A NEURAL NETWORKS ALGORITHM FOR THE MINIMUM COLOURING PROBLEM USING FPGAs

    Article • January 2010, ACTA Press

    Prof. Haidar Harmanani

  24. Geographical Structure of the Y-chromosomal Genetic Landscape of the Levant: A coastal-inland contrast

    Article • Annals of Human Genetics, November 2009, Wiley

    Prof. Haidar Harmanani

  25. A hybrid heuristic approach to optimize rule-based software quality estimation models

    Article • Information and Software Technology, September 2009, Elsevier

    Prof. Haidar Harmanani

  26. A method for efficient mapping and reliable routing for NoC architectures with minimum bandwidth and area

    Article • June 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  27. Integrating wrapper design, TAM assignment, and test scheduling for SOC test optimization

    Article • June 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  28. An Ant Colony Optimization approach for test pattern generation

    Article • May 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  29. Integrated test scheduling, wrapper design, and TAM assignment for hierarchical SOC

    Article • August 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  30. Test time minimization for system-on-chip with test bus assignment and sizing

    Article • August 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  31. Option pricing during post-crash relaxation times

    Article • Physica A Statistical Mechanics and its Applications, July 2007, Elsevier

    Prof. Haidar Harmanani

  32. A Method for Optimizing Test Bus Assignment and Sizing for System-on-a-Chip

    Article • January 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  33. Test bus assignment, sizing, and partitioning for system-on-chip

    Article • Canadian Journal of Electrical and Computer Engineering, January 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  34. Concurrent BIST Synthesis and Test Scheduling Using Genetic Algorithms

    Article • International Journal of Computers and Applications, January 2007, Taylor & Francis

    Prof. Haidar Harmanani

  35. On Power-Constrained System-On-Chip Test Scheduling Using Precedence Relationships

    Article • June 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  36. POWER-CONSTRAINED SYSTEM-ON-A-CHIP TEST SCHEDULING USING A GENETIC ALGORITHM

    Article • Journal of Circuits System and Computers, June 2006, World Scientific Pub Co Pte Lt

    Prof. Haidar Harmanani

  37. AN EVOLUTIONARY ALGORITHM FOR THE ALLOCATION PROBLEM IN HIGH-LEVEL SYNTHESIS

    Article • Journal of Circuits System and Computers, April 2005, World Scientific Pub Co Pte Lt

    Prof. Haidar Harmanani

  38. A hybrid distributed test generation method using deterministic and genetic algorithms

    Article • January 2005, Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  39. A PARALLEL GENETIC ALGORITHM FOR THE GEOMETRICALLY CONSTRAINED SITE LAYOUT PROBLEM WITH UNEQUAL-SIZE FACILITIES

    Article • International Journal of Computational Intelligence and Applications, December 2004, World Scientific Pub Co Pte Lt

    Prof. Haidar Harmanani

  40. A neural networks algorithm for data path synthesis

    Article • Computers & Electrical Engineering, June 2003, Elsevier

    Prof. Haidar Harmanani

  41. Genetic Algorithm for Solving Site Layout Problem with Unequal-Size and Constrained Facilities

    Article • Journal of Computing in Civil Engineering, April 2002, American Society of Civil Engineers (ASCE)

    Prof. Haidar Harmanani

  42. An Evolutionary Algorithm for Solving the Geometrically Constrained Site Layout Problem

    Article • August 2000, American Society of Civil Engineers (ASCE)

    Prof. Haidar Harmanani

  43. Power-Constrained System-on-a-Chip Test-Scheduling Using a Genetic Algorithm

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  44. An evolutionary algorithm for the testable allocation problem in high-level synthesis

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  45. Test insertion at the RT level using functional test metrics

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani

  46. A genetic algorithm for testable data path synthesis

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Prof. Haidar Harmanani