Mr. ASHISH SHARMA
Current affiliation: Malaviya National Institute of Technology Jaipur
Subject: Engineering & Technology
Primary location: India
Sigma-n LBDR: Generic Congestion Handling Routing Implementation for 2D mesh NoC
Published in:IET Computers & Digital Techniques
Publication date:2016-09-01
A framework for thermal aware reliability estimation in 2D NoC
Published in:2015 19th International Symposium on VLSI Design and Test
Publication date:2015-06-01
Characterizing impacts of multi-Vt routers on power and reliability of Network-on-Chip
Published in:2015 Eighth International Conference on Contemporary Computing (IC3)
Publication date:2015-08-01
Network-on-chip: Current issues and challenges
Published in:2015 19th International Symposium on VLSI Design and Test
Publication date:2015-06-01
Improved Route Selection Approaches using Q-learning framework for 2D NoCs
Published in:Proceedings of the 3rd International Workshop on Many-core Embedded Systems - MES '15
Publication date:2015-01-01
Reducing FIFO buffer power using architectural alternatives at RTL
Published in:2016 20th International Symposium on VLSI Design and Test (VDAT)
Publication date:2016-05-01
A Power, Thermal and Reliability-Aware Network-on-Chip
Published in:2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)
Publication date:2017-12-01