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  1. Mitigating Cache Contention-Based Attacks by Logical Associativity

    Article • June 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  2. Using Formal Methods to Evaluate Hardware Reliability in the Presence of Soft Errors

    Article • June 2022, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  3. A Survey on the Susceptibility of PUFs to Invasive, Semi-Invasive and Noninvasive Attacks: Challenges and Opportunities for Future Directions

    Article • Journal of Circuits System and Computers, March 2021, World Scientific Pub Co Pte Lt

    Mark Zwolinski

  4. Learning-based BTI stress estimation and mitigation in multi-core processor systems

    Article • Microprocessors and Microsystems, March 2021, Elsevier

    Mark Zwolinski

  5. Anomaly Detection in an Embedded System

    Article • October 2020, Springer Science + Business Media

    Mark Zwolinski

  6. A Cost-Efficient Aging Sensor Based on Multiple Paths Delay Fault Monitoring

    Article • October 2019, Springer Science + Business Media

    Mark Zwolinski

  7. Ageing Mitigation Techniques for SRAM Memories

    Article • October 2019, Springer Science + Business Media

    Mark Zwolinski

  8. Ageing-Aware Logic Synthesis

    Article • October 2019, Springer Science + Business Media

    Mark Zwolinski

  9. Aging Mitigation Techniques for Microprocessors Using Anti-aging Software

    Article • October 2019, Springer Science + Business Media

    Mark Zwolinski

  10. A reliable PUF in a dual function SRAM

    Article • Integration, September 2019, Elsevier

    Mark Zwolinski

  11. Two-Stage Architectures for Resilient Lightweight PUFs

    Article • July 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  12. Using Hardware Performance Counters to Detect Control Hijacking Attacks

    Article • July 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  13. VLSI Implementation of a Fully-Pipelined K-Best MIMO Detector with Successive Interference Cancellation

    Article • Circuits Systems and Signal Processing, March 2019, Springer Science + Business Media

    Mark Zwolinski

  14. Editorial TVLSI Positioning—Continuing and Accelerating an Upward Trajectory

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, February 2019, Institute of Electrical & Electronics Engineers (IEEE)

    Dr Aida Todri, Dr Baker Mohammad, Mark Zwolinski

  15. Fault Analysis in Analog Circuits Through Language Manipulation and Abstraction

    Article • December 2018, Springer Science + Business Media

    Mark Zwolinski

  16. A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic

    Article • December 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  17. Lifetime Reliability-Aware Digital Synthesis

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, November 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  18. Cell Flipping with Distributed Refresh for Cache Ageing Minimization

    Article • October 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  19. A Machine Learning Attacks Resistant Two Stage Physical Unclonable Functions Design

    Article • July 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  20. A Reliable PUF in a Dual Function SRAM

    Article • July 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  21. Hardware Implementation of a Low-Power K-Best MIMO Detector Based on a Hybrid Merge Network

    Article • July 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  22. Multi-Path Aging Sensor for Cost-Efficient Delay Fault Prediction

    Article • IEEE Transactions on Circuits & Systems II Express Briefs, April 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  23. Cost-efficient design for modeling attacks resistant PUFs

    Article • March 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  24. Early detection of system-level anomalous behaviour using hardware performance counters

    Article • March 2018, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  25. BTI mitigation by anti-ageing software patterns

    Article • Microelectronics Reliability, December 2017, Elsevier

    Mark Zwolinski

  26. Fault analysis in analog circuits through language manipulation and abstraction

    Article • September 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  27. Hardware performance counters for system reliability monitoring

    Article • July 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  28. Lightweight obfuscation techniques for modeling attacks resistant PUFs

    Article • July 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  29. An ageing-aware digital synthesis approach

    Article • June 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  30. A cost-efficient delay-fault monitor

    Article • May 2017, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  31. Overview of PUF-based hardware security solutions for the internet of things

    Article • October 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  32. Sigma-n LBDR: Generic Congestion Handling Routing Implementation for 2D mesh NoC

    Article • IET Computers & Digital Techniques, September 2016, the Institution of Engineering and Technology (the IET)

    Dr V Laxmi, Mark Zwolinski, Mr. ASHISH SHARMA, Professor Manoj Singh Gaur

  33. Guest Editorial

    Article • IET Computers & Digital Techniques, September 2016, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  34. Using I<inf>ddt</inf> current degradation to monitor ageing in CMOS circuits

    Article • September 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  35. NBTI aging evaluation of PUF-based differential architectures

    Article • July 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  36. High accuracy implementation of Adaptive Exponential integrated and fire neuron model

    Article • July 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  37. The European Masters in Embedded Computing Systems (EMECS)

    Article • May 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  38. The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator

    Article • May 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  39. A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, May 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  40. SystemC-AMS Simulation of Conservative Behavioral Descriptions

    Article • January 2016, Springer Science + Business Media

    Mark Zwolinski

  41. IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices

    Article • IEEE Access, January 2016, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  42. Resilient routing implementation in 2D mesh NoC

    Article • Microelectronics Reliability, January 2016, Elsevier

    Mark Zwolinski

  43. A Survey of VLSI Implementations of Tree Search Algorithms for MIMO Detection

    Article • Circuits Systems and Signal Processing, December 2015, Springer Science + Business Media

    Mark Zwolinski

  44. Improved adaptive routing for networks‐on‐chip

    Article • Electronics Letters, December 2015, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  45. VLSI implementation of a scalable K-best MIMO detector

    Article • October 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  46. An application-specific NBTI ageing analysis method

    Article • September 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  47. A framework for thermal aware reliability estimation in 2D NoC

    Article • June 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mr. ASHISH SHARMA, Mark Zwolinski

  48. Network-on-chip: Current issues and challenges

    Article • June 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mr. ASHISH SHARMA, Mark Zwolinski

  49. Reliability analysis of comparators

    Article • June 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  50. TCO-PUF: A subthreshold physical unclonable function

    Article • June 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  51. σLBDR: Congestion-aware logic based distributed routing for 2D NoC

    Article • June 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  52. Parallel Sparse Matrix Solution for Circuit Simulation on FPGAs

    Article • IEEE Transactions on Computers, April 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  53. Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, March 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  54. Conservative behavioural modelling in systemc-AMS

    Article • January 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  55. CERI: Cost-Effective Routing Implementation Technique for Network-on-Chip

    Article • January 2015, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  56. Fault tolerant routing implementation mechanism for irregular 2D mesh NoCs

    Article • October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  57. Fault tolerant and highly adaptive routing for 2D NoCs

    Article • October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  58. A novel non-minimal turn model for highly adaptive routing in 2D NoCs

    Article • October 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  59. A novel non-minimal/minimal turn model for highly adaptive routing in 2D NoCs

    Article • September 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  60. A cost-efficient self-checking register architecture for radiation hardened designs

    Article • June 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  61. Monte Carlo Static Timing Analysis with statistical sampling

    Article • Microelectronics Reliability, February 2014, Elsevier

    Mark Zwolinski

  62. Multivoltage Aware Resistive Open Fault Model

    Article • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, February 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  63. A low-cost radiation hardened flip-flop

    Article • January 2014, EDAA

    Mark Zwolinski

  64. Efficient simulation and modelling of non-rectangular NoC topologies

    Article • January 2014, EDAA

    Mark Zwolinski

  65. A low-cost radiation hardened flip-flop

    Article • January 2014, EDAA

    Mark Zwolinski

  66. Efficient simulation and modelling of non-rectangular NoC topologies

    Article • January 2014, EDAA

    Mark Zwolinski

  67. Highly adaptive and congestion-aware routing for 3D NoCs

    Article • January 2014, ACM (Association for Computing Machinery)

    Mark Zwolinski

  68. CARM: Congestion Adaptive Routing Method for On Chip Networks

    Article • January 2014, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  69. Evaluating system security using Transaction Level Modelling

    Article • Facta universitatis - series Electronics and Energetics, January 2014, National Library of Serbia

    Mark Zwolinski

  70. Energy-Conscious Turbo Decoder Design: A Joint Signal Processing and Transmit Energy Reduction Approach

    Article • IEEE Transactions on Vehicular Technology, October 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  71. On testing of MEDA based digital microfluidics biochips

    Article • August 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  72. An improved instruction-level energy model for RISC microprocessors

    Article • June 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  73. Circuit simulation using state space equations

    Article • June 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  74. Modeling the effect of process variations on the delay and power of the digital circuit using fast simulators

    Article • May 2013, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  75. Oscillation-based analog diagnosis using artificial neural networks based inference mechanism

    Article • Computers & Electrical Engineering, February 2013, Elsevier

    Mark Zwolinski

  76. Circuit Transient Analysis Using State Space Equations

    Article • January 2013, Springer Science + Business Media

    Mark Zwolinski

  77. VLSI Design and Test

    Article • January 2013, Springer Science + Business Media

    Mark Zwolinski

  78. SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems

    Article • June 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  79. A GPU based simulation platform for adaptive frequency hopf oscillators

    Article • May 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  80. <title>Analysis, quantification, and mitigation of electrical variability due to layout dependent effects in SOC designs</title>

    Article • March 2012, SPIE

    Mark Zwolinski

  81. A Large Scale Digital Simulation of Spiking Neural Networks (SNN) on Fast SystemC Simulator

    Article • March 2012, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  82. Reducing the Active Paths Interference in the Chialvo-Bak“Minibrain” Model

    Article • International Journal of Modeling and Optimization, January 2012, IACSIT Press

    Mark Zwolinski

  83. Acceleration of packet filtering using gpgpu

    Article • November 2011, ACM (Association for Computing Machinery)

    Mark Zwolinski

  84. Parallelizing TUNAMI-N1 Using GPGPU

    Article • September 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  85. Radiation hardening by design: A novel gate level approach

    Article • June 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  86. Timing Vulnerability Factors of Ultra Deep-sub-micron CMOS

    Article • May 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  87. On the VLSI Implementation of Adaptive-Frequency Hopf Oscillator

    Article • IEEE Transactions on Circuits and Systems I Regular Papers, May 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  88. Fixed-point multiplication: A probabilistic bit-pattern view

    Article • Microelectronics Reliability, April 2011, Elsevier

    Mark Zwolinski

  89. Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis

    Article • March 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  90. Acceleration of Functional Validation Using GPGPU

    Article • January 2011, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  91. Modelling Smart Card Security Protocols in SystemC TLM

    Article • December 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  92. Very large scale integration architecture for integer wavelet transform

    Article • IET Computers & Digital Techniques, November 2010, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  93. A communication infrastructure for a million processor machine

    Article • May 2010, ACM (Association for Computing Machinery)

    Mark Zwolinski

  94. Design metrics for RTL level estimation of delay variability due to intradie (random) variations

    Article • May 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  95. Parallel sparse matrix solver for direct circuit simulations on FPGAs

    Article • May 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  96. Multi-threaded circuit simulation using OpenMP

    Article • February 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  97. A modified Izhikevich model for circuit implementation of spiking neural networks

    Article • February 2010, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  98. Optimising physical wires usage in mesh-based multi-FPGA systems using partition swapping

    Article • December 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  99. Efficient and realistic statistical worst case delay computation using VHDL

    Article • Electrical Engineering, November 2009, Springer Science + Business Media

    Mark Zwolinski

  100. Physical realizable circuit structure for adaptive frequency Hopf oscillator

    Article • June 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  101. Analytical transient response and propagation delay model for nanoscale CMOS inverter

    Article • May 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  102. Variation resilient adaptive controller for subthreshold circuits

    Article • April 2009, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  103. New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits

    Article • Microelectronics Reliability, February 2009, Elsevier

    Mark Zwolinski

  104. Impact of NBTI on the performance of 35nm CMOS digital circuits

    Article • October 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  105. Behavioural Modelling for Stability of CMOS SRAM Cells Subject to Random Discrete Doping

    Article • September 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  106. On the probability distribution of fixed-point multiplication

    Article • August 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  107. Closed-loop multivariable process identification in the frequency domain

    Article • July 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  108. Symbolic noise analysis approach to computational hardware optimization

    Article • June 2008, ACM (Association for Computing Machinery)

    Mark Zwolinski

  109. Path switching: a technique to tolerate dual rail routing imbalances

    Article • Design Automation for Embedded Systems, May 2008, Springer Science + Business Media

    Mark Zwolinski

  110. New concepts of worst-case delay evaluation in asynchronous VLSI SoC

    Article • May 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  111. Delay fault modelling/simulation using VHDL-AMS in multi-Vdd systems

    Article • May 2008, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  112. General and Technical Program Chairs' Message

    Article • December 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  113. Testing of Level Shifters in Multiple Voltage Designs

    Article • December 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  114. A Symbolic Noise Analysis Approach to Word-Length Optimization in DSP Hardware

    Article • September 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  115. A novel self-routing reconfigurable fault-tolerant cell array

    Article • August 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  116. Multiple-Width Bus Partitioning Approach to Datapath Synthesis

    Article • May 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  117. Using neural networks as a fault detection mechanism in MEMS devices

    Article • Microelectronics Reliability, January 2007, Elsevier

    Mark Zwolinski

  118. Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure

    Article • January 2007, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  119. On the Design of Self-Checking Controllers with Datapath Interactions

    Article • IEEE Transactions on Computers, November 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  120. An Integrated High-Level On-Line Test Synthesis Tool

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, November 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  121. Analogue electronic circuit diagnosis based on ANNs

    Article • Microelectronics Reliability, August 2006, Elsevier

    Mark Zwolinski

  122. Reversible Logic to Cryptographic Hardware: A New Paradigm

    Article • August 2006, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  123. FROM SELF-TEST TO SELF-REPAIR

    Article • IFAC Proceedings Volumes, January 2006, Elsevier

    Mark Zwolinski

  124. Behavioural synthesis of an adaptive Viterbi decoder

    Article • January 2005, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  125. Area word-length trade off in DSP algorithm implementation and optimization

    Article • January 2005, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  126. Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

    Article • Analog Integrated Circuits and Signal Processing, May 2004, Springer Science + Business Media

    Mark Zwolinski

  127. Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

    Article • Journal of Electronic Testing, February 2004, Springer Science + Business Media

    Mark Zwolinski

  128. Concurrent analogue fault simulation, the equation formulation aspect

    Article • International Journal of Circuit Theory and Applications, January 2004, Wiley

    Mark Zwolinski

  129. Behavioural synthesis utilising dynamic memory constructs

    Article • IEE Proceedings - Computers and Digital Techniques, January 2004, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  130. Integrating testability with design space exploration

    Article • Microelectronics Reliability, May 2003, Elsevier

    Mark Zwolinski

  131. Globally convergent algorithms for dc operating point analysis of nonlinear circuits

    Article • IEEE Transactions on Evolutionary Computation, February 2003, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  132. Analysis of mirror mismatch and clock-feedthrough in Bruton transformation switched current wave filters

    Article • IEE Proceedings - Circuits Devices and Systems, January 2003, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  133. A technique for transparent fault injection and simulation in VHDL

    Article • Microelectronics Reliability, June 2001, Elsevier

    Mark Zwolinski

  134. Mutual information theory for adaptive mixture models

    Article • IEEE Transactions on Pattern Analysis and Machine Intelligence, April 2001, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  135. Applying mutual information theory to behavioural analogue fault modelling

    Article • International Journal of Electronics, December 2000, Taylor & Francis

    Mark Zwolinski

  136. Synthesis system for analog circuits

    Article • October 2000, SPIE

    Mark Zwolinski

  137. Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis

    Article • IEE Proceedings - Computers and Digital Techniques, January 2000, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  138. Applying a robust heteroscedastic probabilistic neural network to analog fault detection and classification

    Article • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 2000, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  139. In-line test of synthesised systems exploiting latency analysis

    Article • IEE Proceedings - Computers and Digital Techniques, January 2000, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  140. Applying Mutual Information to Adaptive Mixture Models

    Article • January 2000, Springer Science + Business Media

    Mark Zwolinski

  141. Using robust adaptive mixing for statistical fault macromodelling

    Article • IEE Proceedings - Circuits Devices and Systems, January 2000, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  142. Simulation of losses in resonant converter circuits

    Article • International Journal of Electronics, June 1999, Taylor & Francis

    Mark Zwolinski

  143. Bootstrap, an alternative to Monte Carlo simulation

    Article • Electronics Letters, January 1998, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  144. Article • Analog Integrated Circuits and Signal Processing, January 1998, Springer Science + Business Media

    Mark Zwolinski

  145. A DFT technique to increase the resolution of AC RMS power supply current monitoring of complex analogue circuits

    Article • January 1997, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  146. Analogue circuit synthesis from performance specifications

    Article • January 1997, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  147. Design for test technique for increasing the resolution of supply current monitoring in analogue circuits

    Article • Electronics Letters, January 1997, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  148. Issues in the design of a logic simulator: element modelling for efficiency

    Article • IEE Proceedings - Circuits Devices and Systems, January 1996, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  149. Electrically conductive adhesives for surface mount solder replacement

    Article • IEEE Transactions on Components Packaging and Manufacturing Technology Part C, January 1996, Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  150. Macromodel of CMOS operational amplifier including supply current variation

    Article • Electronics Letters, August 1995, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  151. Anatomy of a simulation backplane

    Article • IEE Proceedings - Computers and Digital Techniques, January 1995, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  152. Issues in the design of a logic simulator: an improved caching technique for event-queue management

    Article • IEE Proceedings - Circuits Devices and Systems, January 1995, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  153. Behavioural macromodelling for analogue fault simulation

    Article • January 1995, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  154. Overview of SPICE-like circuit simulation algorithms

    Article • IEE Proceedings - Circuits Devices and Systems, January 1994, the Institution of Engineering and Technology (the IET)

    Mark Zwolinski

  155. Interleaving: an additional topological compaction technique for Weinberger array generation

    Article • Computer-Aided Design, March 1992, Elsevier

    Mark Zwolinski

  156. Confidence in mixed-mode circuit simulation

    Article • Computer-Aided Design, February 1992, Elsevier

    Mark Zwolinski

  157. Lee router modified for global routing

    Article • Computer-Aided Design, June 1990, Elsevier

    Mark Zwolinski

  158. Use of Existing Cell Library and Software Tools in a Silicon Compilation Environment

    Article • International Journal of Electrical Engineering Education, January 1989, SAGE Publications

    Mark Zwolinski

  159. Using Ella as a Design Tool

    Article • International Journal of Electrical Engineering Education, January 1989, SAGE Publications

    Mark Zwolinski

  160. Divided Backend Duplication Methodology for Balanced Dual Rail Routing

    Article • Springer Science + Business Media

    Mark Zwolinski

  161. Relaxation methods for analogue fault simulation

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  162. Fault Diagnosis in Digital Part of Mixed-Mode Circuit

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  163. Dynamic Voltage Scaling Aware Delay Fault Testing

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  164. Word-Length Oriented Multiobjective Optimization of Area and Power Consumption in DSP Algorithm Implementation

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  165. Behavioural Modelling, Simulation, Test and Diagnosis of MEMS using ANNs

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  166. ANN based modeling, testing and diagnosis of MEMS

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  167. Behavioural modelling of analogue faults in VHDL-AMS - a case study

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  168. DC operating point analysis using evolutionary computing

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  169. Integrating self testability with design space exploration by a controller based estimation technique

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  170. Foundation of combined datapath and controller self-checking design

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  171. The continuous-discrete interface - What does this really mean? Modelling and simulation issues

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  172. Versatile high-level synthesis of self-checking datapaths using an on-line testability metric

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  173. Using evolutionary and hybrid algorithms for DC operating point analysis of nonlinear circuits

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  174. Behavioural modelling of operational amplifier faults using VHDL-AMS

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  175. Transformation based insertion of on-line testing resources in a high-level synthesis environment

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  176. Practical algorithms for fully decoupled mixed-mode simulation of electronic circuits

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  177. Process variation independent built-in current sensor for analogue built-in self-test

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  178. Behavioural modelling of operational amplifier faults using analogue hardware description languages

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  179. Analog circuit synthesis with over-designed circuits

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  180. Fast, robust DC and transient fault simulation for nonlinear analogue circuits

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  181. Testing analog circuits by supply voltage variation and supply current monitoring

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  182. A design for test technique to increase the resolution of analogue supply current tests

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  183. Generation and verification of tests for analogue circuits subject to process parameter deviations

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski

  184. Analogue fault modelling and simulation for supply current monitoring

    Article • Institute of Electrical & Electronics Engineers (IEEE)

    Mark Zwolinski